The introduction of double and triple patterning tightened the Overlay current nodes’ specifications across the industry to levels of 5nm and 3nm respectively. Overlay error is a combination of Intra-field and field-to-field errors. The Intra-field error includes several systematic signatures, such as overlay magnitude differences between X and Y axes, field center vs edge and more. The recent developments in scanner technology improved the intra-field Overlay to high orders. In this work we have quantified the state-of-the-art residual overlay errors and applied the RegC® (registration/overlay control) process, a new solution of deep sub-nanometer pattern shift, to further improve the overlay process control, in addition to the current lithography’s state-of-the-art capabilities. As a result we managed to reduce the baseline overlay error by more than one nanometer and reduced systematic intrafield non-uniformities, by removing the 3 sigma difference between X and Y to zero. The combination of intra-field control by RegC® with high order correction per exposure (CPE) by the scanner provides a new era of overlay control required for the 2x and 1x multiple patterning processes.
Monitoring and control of the various processes in the semiconductor require precise metrology of relevant features. Optical Critical Dimension metrology (OCD) is a non-destructive solution, offering the capability to measure profiles of 2D and 3D features. OCD has an intrinsic averaging over a larger area, resulting in good precision and suppression of local variation. We have studied the feasibility of process monitoring and control in AEI (after etch inspection) applications, using the same angular resolved scatterometer as used for CD, overlay and focus metrology in ADI (after develop inspection) applications1. The sensor covers the full azimuthal-angle range and a large angle-of-incidence range in a single acquisition. The wavelength can be selected between 425nm and 700nm, to optimize for sensitivity for the parameters of interest and robustness against other process variation. In this paper we demonstrate the validity of the OCD data through the measurement and comparison with the reference metrology of multiple wafers at different steps of the imec N14 fabrication process in order to show that this high precision OCD tool can be used for process monitoring and control.
KEYWORDS: Optical alignment, Etching, Back end of line, Metals, Copper, Double patterning technology, Chemical mechanical planarization, Scanners, Neodymium, Optical lithography
For the 14nm node and beyond there are many integration strategy decisions that need to be made. All of these can have a significant impact on both alignment and overlay capability and need to be carefully considered from this perspective. One example of this is whether a Litho Etch Litho Etch (LELE) or a Self Aligned Double Patterning (SADP) process is chosen. The latter significantly impacting alignment and overlay mark design. In this work we look at overlay performance for a Back End of Line (BEOL) SADP Dual Damascene (DD) process for the 14nm node. We discuss alignment mark design, particularly focusing on the added complexity and issues involved in using such a process, for example design of the marks in the Metal Core and Keep layers and recommend an alignment scheme for such an integration strategy.
For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to
achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).
Roughness transfer from Litho to Etch has been evaluated. The impact of Line width roughness (LWR) or Line edge
roughness (LER) is getting larger with shrink of semiconductor devices. In this study, the roughness measurement by
using a single frame SEM image was brought in to avoid resist shrinkage, and image enhance technique is used to
compensate low S/N ratio in this one frame image. CD-AFM was used as reference, and LWR measured by CD-AFM
was compared to the results of one frame enhanced image taken by CD-SEM. And roughness spectrum analysis was
used for evaluation of roughness characteristics taken by CD-SEM and CD-AFM, and its transition by resist shrink or by
etching process. It was enabled to observe the resist roughness profile with minimum shrink by using one frame
enhanced image, then roughness transfer between Litho and Etch was evaluated by comparing in exactly the same
position as pre- and post-etch. As a result, it was confirmed that transferred roughness by etching was remaining the peak
and valley profile in resist observed by CD-SEM, but the roughness amplitude was reduced in higher frequency domain.
This result consists with the roughness characteristics comparison from Litho to Etch. This also means roughness
characteristics analysis shows the actual nanoscopic event.
Line-end gap measurement for OPC calibration is a challenge for metrology. Even for CD-SEM, the rounded shape of
the line end makes it very difficult to measure precisely. We have presented preliminary results of the application of
scatterometry to these challenging structures using an angle resolved polarized scatterometer: ASML YieldStar [1]. In
this paper, the exercise was extended to several different structures combining multiple line-end gap situations.
Systematic comparison with CD-SEM is performed and discussed. Lithographic behavior of the main parameters is
analyzed. Strengths and limits of the technique will be shown. Once validated, the metrology is used to build an OPC
model and correct our test vehicle.
We studied the potential of optical scatterometry to measure the full 3D profile of features representative to
real circuit design topology. The features were selected and printed under conditions to improve the
measurability of the features by scatterometry without any loss of information content for litho monitoring
and control applications. The impact of the scatterometry recipe and settings was evaluated and optimal
settings were determined.
We have applied this strategy on a variety of structures and gathered results using the YieldStar angular
reflection based scatterometer. The reported results show that we obtained effective decoupling of the
measurement of the 3 dimensions of the features. The results match with predictions by calibrated
lithographic simulations.
As a verification we have successfully performed a scanner matching experiment using computational
Pattern Matcher (cPM) in combination with YieldStar as a metrology tool to characterize the difference
between the scanners and verify the matching. The results thus obtained were better than using CD-SEM
for matching and verification.
Overlay metrology performance is usually reported as repeatability, matching between tools or optics aberrations
distorting the measurement (Tool induced shift or TIS). Over the last few years, improvement of these metrics by the
tool suppliers has been impressive. But, what about accuracy? Using different target types, we have already reported
small differences in the mean value as well as fingerprint [1]. These differences make the correctables questionable.
Which target is correct and therefore which translation, scaling etc. values should be fed back to the scanner?
In this paper we investigate the sources of these differences, using several approaches. First, we measure the response of
different targets to offsets programmed in a test vehicle. Second, we check the response of the same overlay targets to
overlay errors programmed into the scanner. We compare overlay target designs; what is the contribution of the size of
the features that make up the target? We use different overlay measurement techniques; is DBO (Diffraction Based
Overlay) more accurate than IBO (Image Based Overlay)? We measure overlay on several stacks; what is the stack
contribution to inaccuracy? In conclusion, we offer an explanation for the observed differences and propose a solution to
reduce them.
Optical bright field wafer inspection followed by repeater analysis is used to find a maximum number of programmed
and natural defects on a EUV patterned mask. Each aspect of the inspection methodology affecting the sensitivity of the
wafer inspection is optimized individually. A special focus is given to the wafer stack. Simulation is used to predict the
optimum stack properties and experimental verification is performed through exposures on the IMEC EUV Alpha Demo
Tool. The final result is benchmarked against state-of-the-art patterned mask inspection and blank inspection to evaluate
the capabilities and limitations of the optical wafer inspection. In addition, the locations obtained by each inspection
technique (wafer and mask) were reviewed on wafer by means of a new automated methodology that is based on a tight
stage accuracy of both inspection tool and review SEM.
EUV lithography is a candidate for device manufacturing for the 16nm node and beyond. To prepare for insertion into
manufacturing, the challenges of this new technology need to be addressed. Therefore, the ASML NXE:3100 preproduction
tool was installed at imec replacing the ASML EUV Alpha Demo Tool (ADT). Since the technology has
moved to a pre-production phase, EUV technology has to mature and it needs to meet the strong requirements of sub
16nm devices. We discuss the CD uniformity and overlay performance of the NXE:3100. We focus on EUV specific
contributions to CD and overlay control, that were identified in earlier work on the ADT. The contributions to overlay
originate from the use of vacuum technology and reflective optics inside the scanner, which are needed for EUV light
transmission and throughput. Because the optical column is in vacuum, both wafer and reticle are held by electrostatic
chucks instead of vacuum chucks and this can affect overlay. Because the reticle is reflective, any reticle (clamp)
unflatness directly translates into a distortion error on wafer (non-telecentricity). For overlay, the wafer clamping
performance is not only determined by the exposure chuck, but also by the wafer type that is used. We will show wafer
clamping repeatability with different wafer types and discuss the thermal stability of the wafer during exposure.
In state of the art production, in order to obtain the best possible overlay performance between critical layers, wafers are
often dedicated to one scanner and all layers processed on that scanner, and in the case of scanners with dual stages, this
often extends to stage dedication as well. Meeting the overlay performance requirements becomes even more complex
with the introduction of EUV lithography into production. It will not be possible to expose all critical layers on an EUV
scanner, which will only be used for some of the most critical layers, the other critical layers will remain on 193nm
immersion scanners. It therefore needs to be demonstrated that the same overlay performance is achievable when tool
types are mixed and matched as when we run with tool dedication. To do this it is critical that we understand the overlay
matching characteristics of 193nm immersion and EUV scanners and from this learn how to control them, so that the
optimum strategy can be developed and overlay errors between these tool types minimized.
In this work we look at the matching performance between two generations of 193nm immersion scanner and an EUV
pre-production tool. We evaluate the matching in both directions, first layer on immersion, second layer on EUV and
vice-versa, and demonstrate how optimum matching can be achieved, so that insertion of an EUV scanner into
production for the required imaging does not result in a degraded overlay capability. We discuss the difference in grid
and intrafield signatures between the tool types and how this knowledge can be used to minimize the overlay errors
between them and if there are any new concerns which impact the chosen strategy when the two tool types are mixed
and matched.
KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Reticles, Data modeling, Calibration, Motion models, Control systems, Optical lithography, Current controlled current source
The tightening of overlay budgets forces us to revisit the characterization and control of exposure tools to eliminate
remaining systematic errors. Even though field-to-field overlay has been a known characterization and control technique
for quite some time, there is still room to further explore and exploit the technique. In particular, it can be used to
characterize systematic errors in a scanner's dynamic exposure behavior. In this paper we investigate the modeling of
field-to-field overlay error starting from a scanner point of view. From a set of general equations we show how
systematic dynamic differences between up and down scanned fields can be extracted from field-to-field overlay
measurements in addition to apparent constant effects. We apply our model to characterize scan speed dependent
dynamic behavior and to verify scanner setup.
Metrology on 3D features like line end gap in a SRAM structure is more challenging than on lines and spaces (L/S)
structures. Scatterometry has been widely used on L/S structures and has enabled characterization of lithographic
features providing with critical dimensions (CD) as well as feature height and side wall angle. In this paper, we will
present the application of scatterometry to these challenging structures using an angle resolved polarized scatterometer:
ASML YieldStar S-100. 3D features (line ends, brick walls,...) measurements will be presented. Measurement capability
will be discussed in terms of sensitivity of the parameters of interest and correlation between them leading to a proper
model choice.
In recent years, numerous authors have reported the advantages of Diffraction Based Overlay (DBO) over Image
Based Overlay (IBO), mainly by comparison of metrology figures of merit such as TIS and TMU. Some have even gone
as far as to say that DBO is the only viable overlay metrology technique for advanced technology nodes; 22nm and
beyond. Typically the only reported drawback of DBO is the size of the required targets. This severely limits its effective
use, when all critical layers of a product, including double patterned layers need to be measured, and in-die overlay
measurements are required.
In this paper we ask whether target size is the only limitation to the adoption of DBO for overlay characterization and
control, or are there other metrics, which need to be considered. For example, overlay accuracy with respect to scanner
baseline or on-product process overlay control? In this work, we critically re-assess the strengths and weaknesses of
DBO for the applications of scanner baseline and on-product process layer overlay control. A comprehensive comparison
is made to IBO. For on product process layer control we compare the performance on critical process layers; Gate,
Contact and Metal. In particularly we focus on the response of the scanner to the corrections determined by each
metrology technique for each process layer, as a measure of the accuracy. Our results show that to characterize an
overlay metrology technique that is suitable for use in advanced technology nodes requires much more than just
evaluating the conventional metrology metrics of TIS and TMU.
KEYWORDS: 3D metrology, Metrology, Critical dimension metrology, Lithography, Scatterometry, Scanning electron microscopy, Scatter measurement, 3D modeling, Optical proximity correction, Process control
Metrology on 3D features like contact holes (CH) is more challenging than on lines and spaces (L/S) structures
especially if one wants to have profile information. Scatterometry has been widely used on L/S structures and has
enabled characterization of lithographic features providing with critical dimensions (CD) as well as feature height and
side wall angle. In this paper, we will present the application of scatterometry to the measurement of 3D structures using
an angle resolved polarized scatterometer: ASML YieldStar S-100. Contact hole measurements will be presented and
correlation to standard metrology tools will be shown. Measurement capability will be discussed in terms of
reproducibility, calculation time, sensitivity of the parameters of interest and correlation between them leading to a
proper model choice. Finally initial results on more complex 3D features (line ends, brick walls,...) will be presented.
We have been developing a resist loss measurement function which is based on quantified pattern top roughness. In
order to use practically the resist loss detection function, the PTR index must be calibrated to amount of resist loss.
Furthermore, the evaluation of different chemical formulation and different film thicknesses of the resist is also
required. In this study, we explore the calibration technique of resist loss detection. In order to convert measured PTR
index into amount of resist loss, a reference measurement to pattern height is required. Techniques that can measure
local pattern height are limited to off-line techniques such as AFM or cross-sectional SEM with current technology.
These techniques have a very long Turnaround Time (TAT), and also highly skilled engineer is required, it cannot be
used for in-line processing. Then, we examined the reasonable calibration method by short TAT. At first, the calibration
wafer with changed resist film thickness is exposed using an "open frame" condition. It is measured by an optical film
thickness metrology (FTM) tool and CD-SEM, a conversion factor is determined and converted PTR index of measured
target patterns into resist loss amount. The validity of converted resist loss amount by this method has been proven by
comparing to the resist height obtained by AFM and cross-sectional SEM images. The calibration technique using PTR
index of un-patterned resist allowed us to understand the relationship between un-patterned resist thickness and resist
surface roughness. We have demonstrated a simple and easy way to calibrate pattern resist loss using CD-SEM top-down
images.
In order to achieve pattern shape measurement with CD-SEM, the Model Based Library (MBL) technique is in the
process of development. In this study, several libraries which consisted by double trapezoid model placed in optimum
layout, were used to measure the various layout patterns. In order to verify the accuracy of the MBL photoresist pattern
shape measurement, CDAFM measurements were carried out as a reference metrology. Both results were compared to
each other, and we confirmed that there is a linear correlation between them. After that, to expand the application field of
the MBL technique, it was applied to end-of-line (EOL) shape measurement to show the capability. Finally, we
confirmed the possibility that the MBL could be applied to more local area shape measurement like hot-spot analysis.
Once a process is set-up in an integrated circuit (IC) manufacturer's fabrication environment, any drift in the proximity
fingerprint of the cluster will negatively impact the yield. In complement to the dose, focus and overlay control of the
cluster, it is therefore also of ever growing importance to monitor and maintain the proximity stability (or CD through
pitch behavior) of each cluster.
In this paper, we report on an experimental proximity stability study of an ASML XT:1900i cluster for a 32 nm poly
process from four different angles. First, we demonstrate the proximity stability over time by weekly wafer exposure and
CD through pitch measurements. Second, we investigate proximity stability from tool-to-tool. In a third approach, the
stability over the exposure field (intra-field through-pitch CD uniformity) is investigated. Finally, we verify that
proximity is maintained through the lot when applying lens heating correction.
Monitoring and maintaining the scanner's optical proximity through time, through the lot, over the field, and from toolto-
tool, involves extensive CD metrology through pitch. In this work, we demonstrate that fast and precise CD through
pitch data acquisition can be obtained by scatterometry (ASML YieldStarTM S-100), which significantly reduces the
metrology load.
The results of this study not only demonstrate the excellent optical proximity stability on a XT:1900i exposure cluster for
a 32 nm poly process, but also show how scatterometry enables thorough optical proximity control in a fabrication
environment.
A combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) is used to find as
many as possible printing defects on two different EUV reticles. These multiple inspections result in a total population of
known printing defects on each reticle. The printability of these defects is first confirmed by wafer review on wafers
exposed on the full field ASML Alpha Demo Tool (ADT) at IMEC. Subsequently reticle review is performed on the
corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This
review methodology allows to separate absorber related mask defects and multi layer (ML) related mask defects. In this
investigation the focus is on ML defects, because this type of reticle defects is EUV specific, and not as evolutionary as
absorber defects which can be mitigated in more conventional ways.
This work gives evidence of critical printing ML defects of natural origin, both pits as shallow as 3nm and bumps just
3nm high at the surface. Wafer inspection was the first inspection technique to detect these ML-defects with marginal
surface height distortion, because both state-of-the-art PMI and especially standard BI on the Lasertec M1350 had failed
to detect these defects.
Compared to standard BI, the more advanced Lasertec M7360 is found to have much better sensitivity for printing MLdefects
and our work so far shows no evidence of printing ML defects missed by this tool. Unfortunately it was also
observed that this required sensitivity was only achieved at the cost of an unacceptable nuisance rate, i.e., with a too high
number of detections of non-printing defects. Optical blank inspection is facing major challenges : It needs not only to
find ML defects with height distortions of 3nm and less (and in theory maybe even 0nm), but also it must be able to
disposition between such likely-printing and non-printing defects.
As critical dimension (CD) control requirements increase and process windows decrease, it is now of even higher
importance to be able to determine and separate the sources of CD error in an immersion cluster, in order to correct for
them. It has already been reported that the CD error contributors can be attributed to two primary lithographic
parameters: effective dose and focus. In this paper, we demonstrate a method to extract effective dose and focus, based
on diffraction based optical metrology (scatterometry). A physical model is used to describe the CD variations of a
target with controlled focus and dose offsets. This calibrated model enables the extraction of effective dose and focus
fingerprints across wafer and across scanner exposure field. We will show how to optimize the target design and the
process conditions, in order to achieve an accurate and precise de-convolution over a larger range of focus and dose than
the expected variation of the cluster.
This technique is implemented on an ASML XT:1900Gi scanner interfaced with a Sokudo RF3S track. The systematic
focus and dose fingerprints obtained by this de-convolution technique enable identification of the specific contributions
of the track, scanner and reticle. Finally, specific corrections are applied to compensate for these systematic CD variations and a significant improvement in CD uniformity is demonstrated.
The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a
leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by
comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model
was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate
variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric
parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching.
Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the
estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50%
CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in
a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step,
agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.
With semiconductor technology moving to smaller patterns after the 45nm hp node, introduction of high-NA immersion
lithography progresses, and with it, the challenge of decreasing process latitude. The decreasing lithography tool focus
margin is mentioned as one of the key problems of a high-NA immersion lithography process. Tool focus fluctuation
has an impact on resist pattern shape and not only does CD change, pattern height also decreases. As a result of
previous studies [1][2], it is understood that the resist loss influences pattern formation after etch, and it was confirmed
that resist loss is important for CD control. We observe correlation between the resist top roughness and the resist loss,
and evaluate the resist loss measurement function by quantifying the resist top roughness. This principle of resist loss
detection by measuring roughness is that a changing roughness of resist pattern top is detected as a fluctuation in image
brightness on the CD-SEM. A measurement idea was proposed and performance evaluation has already been performed
by using one kind of sample. In this study, we demonstrate the validity of resist loss detection by investigating various
wafer conditions which contain the dependency by looking at two types of resist and different exposure tool
illumination settings. Furthermore, we have confirmed the sensitivity limit of resist loss detection which is
approximately above 10nm. Finally, we have discussed improving the resist loss detection sensitivity and considered the applicability of resist loss detection for the litho process monitor.
The scatterometry or OCD (Optical CD) metrology technique has in recent years moved from being a general purpose
CD metrology technique to one that addresses the metrology needs of process monitoring and control, where its
strengths can be fully utilized. With the significant advancements that have been made in both hardware and software
design, the setup time required to build complex models and solutions has been significantly reduced. Whilst the
application of scatterometry to process control has clearly shown its merits, the question still arises as to how accurately
the process corrections to feed forward or feedback for process control can be extracted?
In this work we critically examine the accuracy of scatterometry with respect to process control by comparing three
hardware platforms, on a simple litho stack. The impact of hardware design is discussed as well as the 'setup' of the
modeled parameters on the final measurement result. It will be shown that informations extracted based on scatterometry
measurements must be true to process variation and independent of the hardware design. Our results will show that the
ability to use scatterometry effectively for process control ultimately lies in the ability to accurately determine the
changes that have occurred in the process and to be able to extract appropriate process corrections for feedback or feed
forward control; allowing these changes to be accurately corrected. To do this the metrology validation extends beyond
the typical metrology metrics such as precision and TMU; metrology validation with respect to process control must
encompass accurate determination of process corrections to ensure a process tool and/or process stays at the set point.
Defect review of advanced lithography processes is becoming more and more challenging as feature sizes decrease.
Previous studies using a defect review SEM on immersion lithography generated wafers have resulted in a defect
classification scheme which, among others, includes a category for micro-bridges. Micro-bridges are small connections
between two adjacent lines in photo-resist and are considered device killing defects. Micro-bridge rates also tend to
increase as feature sizes decrease, making them even more important for the next technology nodes.
Especially because micro-bridge defects can originate from different root causes, the need to further refine and split up
the classification of this type of defect into sub groups may become a necessity.
This paper focuses on finding the correlation of the different types of micro-bridge defects to a particular root cause
based on a full characterization and root cause analysis of this class of defects, by using advanced SEM review
capabilities like high quality imaging in very low FOV, Multi Perspective SEM Imaging (MPSI), tilted column and
rotated stage (Tilt&Rotation) imaging and Focused Ion Beam (FIB) cross sectioning.
Immersion lithography material has been mainly used to generate the set of data presented in this work even though, in
the last part of the results, some EUV lithography data will be presented as part of the continuing effort to extend the
micro-bridge defect characterization to the EUV technology on 40 nm technology node and beyond.
Numerous metrology tools, techniques and methods are used by the industry to setup and qualify exposure tools for
production. Traditionally, different metrology techniques and tools have been used to setup dose, focus and overlay
optimally and they do so independently. The methods used can be cumbersome, have the potential to interfere with each
other and some even require an unacceptable amount of costly exposure tool time for data acquisition.
In this work, we present a method that uses an advanced angle-resolved scatterometry metrology tool that has the
capability to measure both CD and overlay. By using a technique to de-convolve dose and focus based on the profile
measurement of a well characterized process monitor target, we show that the dose and focus signature of a high NA
193nm immersion scanner can be effectively measured and corrected. A similar approach was also taken to address
overlay errors using the diffraction based overlay capability of our metrology tool. We demonstrate the advantage of having a single metrology tool solution, which enables us to reduce dose, focus and overlay signatures to a minimum.
Diffraction Based Overlay (DBO) metrology has been shown to have significantly reduced Total Measurement
Uncertainty (TMU) compared to Image Based Overlay (IBO), primarily due to having no measurable Tool Induced Shift
(TIS). However, the advantages of having no measurable TIS can be outweighed by increased susceptibility to WIS
(Wafer Induced Shift) caused by target damage, process non-uniformities and variations. The path to optimum DBO
performance lies in having well characterized metrology targets, which are insensitive to process non-uniformities and
variations, in combination with optimized recipes which take advantage of advanced DBO designs.
In this work we examine the impact of different degrees of process non-uniformity and target damage on DBO
measurement gratings and study their impact on overlay measurement accuracy and precision. Multiple wavelength and dual polarization scatterometry are used to characterize the DBO design performance over the range of process variation. In conclusion, we describe the robustness of DBO metrology to target damage and show how to exploit the measurement capability of a multiple wavelength, dual polarization scatterometry tool to ensure the required measurement accuracy for current and future technology nodes.
In a 2009 analysis of microbridging defectivity, a design of experiment methodology was used to show the effect of
filtration parameters on microbridging defectivity, specifically focusing on filter retention rating, filter media and design,
filtration rate, and controlled filtration pressure. In that analysis it was shown that different filter architectures provide
the most effective filtration of microbridging and that different filter architectures show different levels of microbridging
defects even when optimally tuned. Ultimately, filter choice and filtration setup matter in removal of microbridging
defects.
In the new analysis, a similar approach was taken with additional filter types. However, in the new study the retention rating of the filters was kept constant at 10nm while other filter parameters were varied, including membrane material and design. This study will show the specific effect of the membrane material and design on microbridging defectivity in addition to the effects of filtration setup.
As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO
ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby
enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of
Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the
collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing
sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and
defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV
exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution
characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and
defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows
within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives
initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that
while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.
Microbridging defects have emerged as one of the top yield detractor in semiconductor manufacturing as Moore's law
drives towards 32nm processing utilizing immersion lithography. It is generally recognized that there are multiple root
causes for microbridging defectivity. Image and resist contrast and different developer techniques have been studied and
their contribution to microbridging defectivity has been described. In this study we will focus on the effect of point-ofuse
filtration and how it is best used to mitigate microbridging defectivity.
A design of experiment methodology will be utilized to understand the effect of various filter and filtration parameters
on microbridging defectivity, including filter retention rating, filter media and design, filtration rate, and controlled
filtration pressure. It is anticipated that by better understanding the effect of point-of-use filtration on microbridging
defectivity, guidelines for better control of this type of defect may be formulated.
With the improved resolution of immersion lithography by Hyper-NA (Numerical Aperture) and Low-k1 scaling factor,
lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. It is important for
high precision process monitoring the decrease in process latitude which comes with Hyper-NA and Low-k1, in order to
be able to successfully introduce RET (Resolution Enhancement Techniques) lithography into high volume production.
MPPC (Multiple Parameters Profile Characterization) is a function which provides the ability to extract pattern shape
information from a measured e-beam signal. MPPC function becomes key technique of pattern profile verification by
top down SEM images for the Hyper-NA lithography, for that reason it can be detected to relate to pattern profile
change.
In this work, we explored a practical application of MPPC function by making clear the relationship between MPPC
indices and Litho parameters concerning specific lithography application. We performed the two kinds of experiment
for verifying effectiveness of the MPPC function. First experiment explored printing image contrast by using the WB
with exposure pattern shape change related from image printing condition. Second experiment explored pattern shape
change due to resist contrast with changing the process conditions by using WB behavior. In consequence, we
demonstrated a practical application of MPPC function by quantification using WB and assessed the process monitoring
capability.
Our challenge of this research is the practical application of the MPPC function on production wafers concerning
specific lithography application. We believe that this application can be effectual in process monitoring and control for
Hyper-NA lithography.
The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node
and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has
to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also
demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOLTM
[1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the
required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double
patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process
compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT
very challenging.
In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique
(SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double
patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The
process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard
imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer
imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs
already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the
scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We
conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in
double patterning processes.
Ever since the introduction of immersion lithography overlay has been a primary concern. Immersion exposure tools
show an overlay fingerprint that we hope to correct for by introducing correctables per field, i.e. a piece-wise
approximation of the fingerprint but within the correction capabilities of the exposure tool. If this mechanism is to be
used for reducing overlay errors it must be stable over an entire batch. This type of correction requires a substantial
amount of measurements therefore it would be ideal if the fingerprint is also stable over time. These requirements are of
particular importance for double patterning where overlay budgets have been further reduced. Since the variation of the
fingerprint specific to immersion tools creeps directly into the overlay budget, it is important to know how much of the
total overlay error can be attributed to changes in the immersion fingerprint. In this paper we estimate this immersion
specific error but find it to be a very small contributor.
In this study, the principle of the resist loss measurement method proposed in our previous paper[1] was verified. The technique proposes the detection of resist loss variation using the pattern top roughness (PTR) index determined by scanning electron microscope images. By measuring resist loss with atomic force microscope, we confirmed that the PTR showed a good correlation with the resist loss and was capable of detecting variations within an accuracy of 20 nm for the evaluated sample. Furthermore, the effect of PTR monitoring on line width control was evaluated by comparing the error in line width control after eliminating undesirable resist loss patterns to that of conventional line width monitoring. The error of line width control was defined as the deviation range in post-etch line widths from post-litho values. Using PTR monitoring, the error in line width control decreased from 10 nm to less than 3 nm, thus confirming
the effectiveness of this method.
Determination of the optimal double patterning scheme depends on cost, integration complexity, and performance. This
paper will compare the overall CDU performance of litho-etch-litho-etch (LELE) versus a spacer approach. The authors
use Monte Carlo simulation as a way to rigorously account for the effect of each contributor to the overall CD variation
of the double patterning process. Monte Carlo simulation has been applied to determine CD variations in previous
studies1-2, but this paper will extend the methodology into double patterning using a calibrated resist model with
topography.
Double patterning lithography (DPL)-either with two litho and two etches or through the use of a sacrificial spacer-are comparable in complexity and process control requirements. Since critical dimensions uniformity (CDU) and overlay requirements are considerably tighter than in single exposure, they present tougher challenges to process control, metrology, and integration, but seem feasible for 32-nm node. We study CDU and overlay requirements and performance at 32-nm-hp resolution for dual litho-etch and sacrificial spacer schemes. We bring in three particular aspects of CD control: the existence of multiple populations of lines and spaces, overlay entanglement into CDU performance, and the mechanism of doubled-pitch pattern generation from uncorrelated left and right edges, Accordingly, active compensation schemes are proposed to bring together these multiple CDU populations in order to achieve the typical 10% CD tolerance of the final pattern. Experimental results confirmed our assumptions of CDU-overlay entanglement and existence of multiple CD populations of lines and spaces. We present CDU results from before and after applying CD compensation schemes to improve CDU and overlay performance through active feed forward corrections. Results confirm the gain in improving statistical and spatial CD distribution to meet control levels required at 32-nm design rules: 2-nm CDU control per population, 3-nm CDU control for two adjacent lines, or spacer CD populations with 3-nm single machine overlay, all of them being demonstrated on multiple wafers and immersion scanners.
KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Signal detection, Lithography, Signal attenuation, Semiconducting wafers, Process control, 3D metrology, Finite element methods, Metrology
In our previous paper*[1], next generation lithography offering improved resolution by use of Hyper-NA and Low-k1,
changes in exposure tool focus were seen to influence pattern shape and it was verified that pattern profile variation
occurs even when measured CD values are similar. This shows the necessity for process control to include pattern
shape information, conventional methods using the CD value alone will be insufficient as process latitudes continue to
shrink. In such a situation, to be able to precisely measure the physical dimensions of design features becomes more
and more important.
In this study, we have investigated improved precision of Process Window (PW) determination by using the MPPC
function that allows the pattern profile shape to be quantified. We have also evaluated pattern shape variation by
means of Litho-simulation. As a result, it was confirmed that resist loss is the main change in shape that occurs.
Therefore, we have focused our attention on resist loss and optimized the MPPC parameters by SEM simulation*[2].
As a consequence, it was possible to precisely detect the resist loss. Using this technique, it was possible to show the
possibility for highly precise 3D measurement determination, for use in exposure tool monitoring, by using the MPPC
measurement technique.
In this research, we improved litho process monitor performance with CD-SEM for hyper-NA lithography. First, by
comparing litho and etch process windows, it was confirmed that litho process monitor performance is insufficient just
by CD measurement because of litho-etch CD bias variation. Then we investigated the impact of the changing resist
profile on litho-etch CD bias variation by cross-sectional observation. As a result, it was determined that resist loss and
footing variation cause litho-etch CD bias variation. Then, we proposed a measurement method to detect the resist loss
variation from top-down SEM image. Proposed resist loss measurement method had good linearity to detect resist loss
variation. At the end, threshold of resist loss index for litho process monitor was determined as to detect litho-etch CD
bias variation. Then we confirmed that with the proposed resist loss measurement method, the litho process monitor
performance was improved by detection of litho-etch CD bias variation in the same throughput as CD measurement.
Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends
the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense
features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a
double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss
some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus
more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both
simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.
With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay
performance and whether or not this meets the required overlay for double patterning. However, as we require tighter
and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the
achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition
steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay
performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to
follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this
paper we investigate the process impact of various double patterning integration strategies and attempt to show the
importance of selecting the right strategy with respect to achieving a manufacturable double patterning process.
Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process
induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant
process steps.
The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total
measurement uncertainty requirements of 0.57 nm for the most challenging use cases of the 32nm technology generation.
Theoretical considerations show that overlay technology based on differential signal scatterometry (SCOLTM) has
inherent advantages, which will allow it to achieve the 32nm technology generation requirements and go beyond it.
In this work we present results of an experimental and theoretical study of SCOL. We present experimental results,
comparing this technology with the standard imaging overlay metrology. In particular, we present performance results,
such as precision and tool induced shift, for different target designs. The response to a large range of induced
misalignment is also shown. SCOL performance on these targets for a real stack is reported. We also show results of
simulations of the expected accuracy and performance associated with a variety of scatterometry overlay target designs.
The simulations were carried out on several stacks including FEOL and BEOL materials. The inherent limitations and
possible improvements of the SCOL technology are discussed. We show that with the appropriate target design and
algorithms, scatterometry overlay achieves the accuracy required for future technology generations.
Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have
equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to
process control, metrology and integration, but seem feasible for the 32nm node.
In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double
patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific
aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and
spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD
populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple
populations in order to meet comparable 10% CDU as in single exposure.
We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming
capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After
compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and
multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU
populations entangled overlay into CDU.
With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or
larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches
have been used to push even further the resolution limit by reducing k1 scaling factor, including Double Patterning
Technology. However, with the improved resolution by Hyper-NA and Low-k1, lithographers face the problem of
decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been
widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to
accurately and efficiently derive a Process Window within which a process can run on target and in control is
fundamental to Low-k1 lithography. Accuracy of Process Window derivation is based on the ability to accurately
measure and model the physical dimension of the design feature and how it changes in response to changes in process
parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by
changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design
feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is
shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a
FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus
providing higher precision measurement in comparison to the conventional single point measurement. As seen in this
work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability
of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) *1), a
function which provides the ability to extract pattern shape information from a measured e-beam signal. This function
together with the ACD function enables PW measurement with high precision, which also takes into account the actual
pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC
measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.
As device critical dimensions (CD) decrease, they approach the limits of standard metrology techniques and measuring
features smaller than 20 nm represents a serious challenge. Within the framework of the 32 nm program at IMEC, a
reliable and accurate approach to small feature metrology is required. We describe here a methodology aimed at
measuring features down to 10nm by means of scatterometry. The results are compared to calibrated CDSEM
measurements [1]. The active fins of a Multi Gate Field Effect Transistors (MuGFET) was measured across wafer and
across batch. Scribe to cell correlation, wafer fingerprint, 3D profile, oxide thickness were also investigated. In
particular, 3D profile information was compared to TEM. Our approach produced very consistent results for all
measurement techniques (scatterometry, CDSEM and TEM) and it is now fully integrated in the IMEC production line to
monitor the MuGFET platform.
Monitoring of the focus performance is recognized to be an important part of a periodic scanner health check, but can
one simply apply all techniques that have been used for dry scanners to immersion scanners? And if so how do such
techniques compare to scanner self-metrology tests that are used to set up the tool? In this paper we look at one specific
off-line focus characterization technique, Back Side Chrome (BSC), which we then try to match with results obtained
from two self-metrology focus tests, available on the scanner chosen for this work. The latter tests are also used to set up
the immersion scanner. We point out a few concerns, discuss their effect and indicate that for each generation of
immersion tool one should redo the entire exercise.
We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).
KEYWORDS: Metrology, Scanning electron microscopy, Semiconducting wafers, Manufacturing, Finite element methods, Lithography, Resolution enhancement technologies, Design for manufacturing, Electroluminescence, Process control
Resolution enhancement techniques (RET), immersion lithography, and Design for Manufacturing (DFM) are all geared towards increasing the lithographic process window to enable the ever more difficult processing demands of semiconductor manufacturing. It is well understood that there is a trade-off between depth of focus (DOF) and exposure dose latitude (EL), as well as best focus (BF) and best exposure dose (BE), in which a Manufacturable Process Window (MPW) must be established and centered. Oftentimes it is overlooked that this balance needs to be maintained across multiple dimensions including spatial (e.g. across field), density (e.g. dense, iso), temporal, tool-to-tool, etc. To maintain this critical balance, both test wafers and product wafers need to be monitored and analyzed in order to support Advanced Process Control (APC) and Automated Equipment Control (AEC). In this work we establish a method to optimize process window by using an integrated analysis workstation based on measurements from both optical and e-beam metrology. By applying this method, we demonstrate a MPW on daily FEM and nominal wafers already used at IMEC for daily process qualification.
As we move forward to the 45 and 32nm node, MuGFET's (Multi-Gate Field-Effect Transistor) are considered more
and more as a necessary alternative to keep pace with Moore's Law. If proven manufacturable, MuGFET's could
eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive
metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET
metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small
dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated
check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here
some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to
calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way
by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the
application of design-based metrology (DBM) to MuGFET OPC validation.
The immersion effects on lithography-system performance have been investigated using a ASML TWINSCAN XT:1250Di immersion-ArF scanner (NA=0.85) and Tokyo Electron CLEAN TRACK ACT12 at IMEC. Effects of immersion-induced-temperature change and effects of material-top surface are discussed in this paper. The wafer-stage temperature is measured during the leveling-verification tests and compared with the observed residual-focus-error change. The results indicate that stage-temperature change under an immersion environment can induce a focus change. In this paper, it was proved that the improved-temperature-control stage is effective to mitigate the immersion-specific focus change. The immersion effect on overlay is also investigated as a function of material top surface. It was demonstrated that the effect of material-receding-contact angles on the grid-residual errors (non-correctable errors) is small in the latest-immersion-hardware configuration of the scanner. However, there was a tendency that material with a smaller-receding-contact angle has a larger-wafer scaling although it is a correctable parameter. This can be caused by the first-layer wafer shrinkage due to more water evaporation on the more-hydrophilic surface. The immersion effect on scanner-dynamic performance is then investigated by changing the material-top surface and the scan speed of the scanner. It was turned out that the scan synchronization is not much affected by differences of material receding-contact-angles for the new configuration of the scanner. Moving-standard deviation of the synchronization error in scanning direction (y-direction) is slightly more affected by increased scanning speed, although it stays within specification even at a maximum scan speed of 500 mm/sec. Finally the immersion effects on resist-profile uniformity are examined. It was found that lower-leaching-film stacks (with a top coat or a lower leaching resist) seem to mitigate the variation of resist-profile uniformity.
Control of critical dimension (CD) and resist profile is increasingly important in low-k1 lithography, and becomes more difficult in thin resist processing due to the chemical interaction occurring at the resist surfaces. Implementation of immersion lithography will make the control even more challenging since more sources of chemical interaction can play a role, e.g. leaching of photo active material from the resist into the water, or diffusion of the water into the resist. Moreover, the contact of the liquid in the scanner showerhead with the wafer surface is a dynamic and local interaction, which needs to be understood and quantified, since variations in soak time are a possible source of intra-field and across wafer CD-variations. In this paper we developed a methodology to understand and to quantify the impact of immersion scanner soak on resist profile control and CD-control. The methodology is on the one hand based on the simulation of the showerhead movements over the wafer during the immersion lithography process, where for a particular location on the wafer the soak time is calculated by accumulating the interaction time every time the showerhead is passing that particular location. On the other hand the methodology quantifies experimentally how much resist profile change and CD-variation is caused by a particular pre- and post-soak time, by testing the process in a virtual immersion set-up and measuring the CD-response with high-precision scatterometry. In this way, we were able to predict CD-variations related to immersion soak. Using the initial resist and topcoat processes, we recently experimentally verified on the ASML XT:1250Di immersion tool at IMEC that these soak related CD-variations exist. The effects are small, but in line with the soak time simulations and the CD-response obtained on the virtual immersion set-up. This demonstrates that the methodology described above could be very useful to select materials for lithography processes and to set specifications for allowed CD-variations in line with to the over-all allowed CD-budget.
Contact hole lithography presents a variety of challenges for process development. Measurement of the bottom of the hole presents the most difficulty, and metrology error has traditionally been much larger for contact (3D) metrology than for line/space structures. In light of process windows being significantly smaller for contact holes than for line/space structures, it is difficult to maintain good Contact CD characterization of novel methods requires CD correlation to existing metrology tools including CD linearity across a range of pitches and target CDs. In this paper, we will present contact CD linearity results as characterized by integrated ODP scatterometry, where measurements of hole CD and profile have been made following the lithography process, in a method nondestructive to the 193nm resist pattern on the wafer. The CD linearity is characterized for a 90nm technology device film stack of patterned photoresist (PR), bottom anti-reflective coating (BARC), oxide, and SiC on top of a silicon (Si) substrate. The pattern densities range from dense to semi-dense to isolated, and the grating structures include circular holes aligned in an orthogonal pattern on the wafer. Measurement stability results are also shown, and correlation to CD-SEM and cross-section SEM is provided as a reference metrology. The results of the experiment show that ODP can be used successfully to not only characterize contact CD linearity, but to also monitor film thickness and profile variation, providing a valuable solution for contact hole process development.
In recent years scatterometry has been shown to have impressive long term repeatability of better than 1.5nm for simple resist stacks. Equally impressive results have been reported for Shallow Trench Isolation (STI), thus enabling effective monitoring of STI trench etch. These results were achieved by following the methodology that results obtained for a given library must be rigorously tested, to ensure measured results respond correctly to process variation. Following the same methodology, the scatterometry capability for the gate stack after litho and after etch has been evaluated. The stack used is IMEC's standard gate process for the 90 nm node.
After a complete library generation, these results are compared to CD SEM and X SEM. These optimized libraries are used on few wafers with strong etch variations. The response to process variations is shown. A method to qualify and monitor the etch tool is demonstrated.
The accurate measurement of CD (critical dimension) and its application to inline process control are key challenges for high yield and OEE (overall equipment efficiency) in semiconductor production. CD-SEM metrology, although providing the resolution necessary for CD evaluation, suffers from the well-known effect of resist shrinkage, making accuracy and stability of the measurements an issue. For sub-100 nm in-line process control, where accuracy and stability as well as speed are required, CD-SEM metrology faces serious limitations. In contrast, scatterometry, using broadband optical spectra taken from grating structures, does not suffer from such limitations. This technology is non-destructive and, in addition to CD, provides profile information and film thickness in a single measurement. Using Timbre's Optical Digital Profililometry (ODP) technology, we characterized the Process Window, using a iODP101 integrated optical CD metrology into a TEL Clean Track at IMEC. We demonstrate the Optical CD's high sensitivity to process change and its insensitivity to measurement noise. We demonstrate the validity of ODP modeling by showing its accurate response to known process changes built into the evaluation and its excellent correlation to CD-SEM. We will further discuss the intrinsic Optical CD metrology factors that affect the tool precision, accuracy and its correlation to CD-SEM.
For the 100nm technology node, the electrical measurement technique continues to play an important role as a metrology tool for generating large volumes of unbiased and statistically significant CD data. However, the ECD offset of approximately 35 to 40nm between the SEM CD after etch and the electrically measured CD obtained with the current standard ELM process, is a potential limitation for applying ELM to feature sizes below 65nm. Is this ECD offset process related or have we reached the limitation of the metrology technique fundamental to ELM? These are questions we attempt to answer in this paper. This paper attempts to answer these questions by looking at the fundamentals of the metrology technique and the influence of substrate material on the ECD offset. A calibration of the offset is performed by benchmarking ECD against different CD-SEM measurement algorithms. We re-examine the basic assumption that is fundamental to the electrical measurement technique and examine if this still holds true when the CD has become smaller although the substrate thickness has remained constant? In conclusion we report the parameters influencing the ECD to physical measurement bias and the limitations of this measurement technique.
In recent years scatterometry has been shown to demonstrate very impressive long term repeatability of better than 1.5nm when measuring a simple resist stack. However, does this impressive precision hold true for a more complicated stack such as that of Shallow Trench Isolation (STI)? Furthermore what benefits does scatterometry metrology bring compared to CD-SEM and X-SEM metrology for STI characterization and monitoring? In this work, we examine the impact of critical attributes fundamental to scatterometry metrology, such as grating parameter sensitivity and library optimization, for the STI layer of a CMOS process using KLA-Tencor’s SpectroscopicCD. We report the results from an optimized library to characterize the STI process after trench etch and the sensitivity of the metrology will also be discussed. Finally, the efficiency of this technique is demonstrated by reference to the monitoring results for a period of approximately five months.
We formulate a physical model to extract effective dose and defocus (EDD) from pattern profile data and demonstrate its efficacy in the analysis of in-line scatterometer measurements. From the measurement of a single target structure, the model enables simultaneous computation of pattern dimensions pre-calibrated to the imaging system dose and focus settings. Our approach is generally applicable to ensuring the adherence of pattern features to dimensional tolerances in the control and disposition of product wafers while minimizing in-line metrology.
KEYWORDS: Critical dimension metrology, Semiconducting wafers, Lithography, Metrology, Scatterometry, Process control, 193nm lithography, Control systems, Finite element methods, Time metrology
In the continuous drive for smaller feature sizes, process monitoring becomes increasingly important to compensate for the smaller lithography process window and to assure that Critical Dimensions (CD) remain within the required specifications. Moreover, the higher level of automation in manufacturing enables almost real-time correction of lithography cluster machine parameters, resulting in a more efficient and controlled use of the tools. Therefore, fast and precise in-line lithography metrology using Advanced Process Control (APC) rules are becoming crucial, in order to guarantee that critical dimensions stay correctly targeted.
In this paper, the feasibility of improving the CD control of a 193nm lithography cluster has been investigated by using integrated scatterometry. The target of the work was to identify if a dose correction on field and wafer level, based on precise in-line measurements, could improve the overall CD control. Firstly, the integrated metrology has been evaluated extensively towards precision and sensitivity in order to prove its benefits for this kind of control. Having a long-term repeatability of significantly better than 0.75nm 3σ, this was very promising towards the requirements for sub-nanometer CD correction. Moreover, based on an extensive evaluation of the process window on the lithography cluster, it has been shown that the focus variation is minimal and that CD control can be improved using dose correction only. In addition, systematic variations in across-wafer uniformity and across-lot uniformity have been determined during this monitoring period, in order to identify correctable fingerprints. Finally, the dose correction model has been applied to compensate for these systematic CD variations and improved CD control was demonstrated. Using a simple dose correction rule, a forty percent improvement in CD control was obtained.
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