Paper
24 March 2008 Sources of overlay error in double patterning integration schemes
Author Affiliations +
Abstract
With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay performance and whether or not this meets the required overlay for double patterning. However, as we require tighter and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this paper we investigate the process impact of various double patterning integration strategies and attempt to show the importance of selecting the right strategy with respect to achieving a manufacturable double patterning process. Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant process steps.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David Laidler, Philippe Leray, Koen D’havé, and Shaunee Cheng "Sources of overlay error in double patterning integration schemes", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69221E (24 March 2008); https://doi.org/10.1117/12.773575
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CITATIONS
Cited by 27 scholarly publications.
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KEYWORDS
Semiconducting wafers

Optical alignment

Overlay metrology

Double patterning technology

Metrology

Etching

Manufacturing

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