Mr. Eiichi Soda Profile

Eiichi Soda

Researcher at Semiconductor Leading Edge Technologies Inc.

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Publications (6)

Proceedings Article | 23 March 2010 Paper

Fabrication of 35nm via-hole patterns for interconnect test chips with EUV lithography

Yuusuke Tanaka, Hajime Aoyama, Kazuo Tawarayama, Shunko Magoshi, Daisuke Kawamura, Kentaro Matsunaga, Takashi Kamo, Yukiyasu Arisawa, Taiga Uno, Hiroyuki Tanaka, Naofumi Nakamura, Eiichi Soda, Noriaki Oda, Shuichi Saito, Ichiro Mori

Proceedings Volume 7636, 76362D (2010) https://doi.org/10.1117/12.846315

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Optical proximity correction, Metals, Extreme ultraviolet, Semiconducting wafers, Critical dimension metrology, Semiconductors, Anisotropy, Error analysis

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Proceedings Article | 23 March 2010 Paper

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Hajime Aoyama, Yuusuke Tanaka, Kazuo Tawarayama, Naofumi Nakamura, Eiichi Soda, Noriaki Oda, Yukiyasu Arisawa, Taiga Uno, Takashi Kamo, Kentaro Matsunaga, Daisuke Kawamura, Toshihiko Tanaka, Hiroyuki Tanaka, Shuichi Saito, Ichiro Mori

Proceedings Volume 7636, 76361N (2010) https://doi.org/10.1117/12.846325

KEYWORDS: Extreme ultraviolet lithography, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Photomasks, Etching, Photoresist processing, Overlay metrology, Lithography, Scanning electron microscopy

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Proceedings Article | 1 April 2009 Paper

Pattern transfer process development for EUVL

Daisuke Kawamura, Yuusuke Tanaka, Toshiro Itani, Eiichi Soda, Noriaki Oda

Proceedings Volume 7273, 72731O (2009) https://doi.org/10.1117/12.812928

KEYWORDS: Etching, Reactive ion etching, Extreme ultraviolet lithography, Silicon, Manufacturing, System on a chip, Photoresist processing, Scanning electron microscopy, Photomasks, Overlay metrology

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Proceedings Article | 2 April 2007 Paper

Correlation between etching and optical properties of organic films for multilayer resist

E. Soda, F. Koba, S. Kondo, S. Ogawa, S. Saito

Proceedings Volume 6519, 65192P (2007) https://doi.org/10.1117/12.710788

KEYWORDS: Etching, Refractive index, Critical dimension metrology, FT-IR spectroscopy, Silicon, Scanning electron microscopy, Semiconducting wafers, Optical properties, Polymers, Electron beam lithography

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Proceedings Article | 24 March 2006 Paper

Tri-layer resists process for fabricating 45-nm L&S patterns by EPL

Fumihiro Koba, Kazuyuki Matsumaro, Eiichi Soda, Tadayoshi Watanabe, Yoshihisa Matsubara, Hiroshi Arimoto, Tasuku Matsumiya, Daisuke Kawana, Naoki Yamashita, Yasushi Fujii, Katsumi Ohmori, Mitsuru Sato, Takahiro Kozawa, Seiichi Tagawa

Proceedings Volume 6151, 615127 (2006) https://doi.org/10.1117/12.655976

KEYWORDS: Photoresist processing, Failure analysis, Etching, Back end of line, Semiconducting wafers, Critical dimension metrology, Electron beam lithography, Lithography, Extreme ultraviolet lithography, Photomasks

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In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.

Proceedings Article | 6 May 2005 Paper

EPL performance in 65-nm node metallization technology and beyond

F. Koba, T. Tsuchida, H. Sakaue, K. Koike, J. Yamamoto, N. Iriki, H. Yamashita, S. Kageyama, T. Nasuno, E. Soda, K. Takeda, H. Kobayashi, F. Shoji, H. Okamura, Y. Matsubara, H. Arimoto

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.599257

KEYWORDS: Metals, Transmission electron microscopy, Lithography, Scanners, Copper, Scanning electron microscopy, Resistance, Electron beam lithography, Overlay metrology, Chemical mechanical planarization

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