Mr. Kazuyuki Matsumaro Profile

Kazuyuki Matsumaro

at National Institute of Advanced Industrial Science

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Author

Publications (6)

Proceedings Article | 8 April 2011 Paper

Relationships between EUV resist outgassing and contamination deposition at Selete

Hiroaki Oizumi, Kazuyuki Matsumaro, Satoshi Nomura, Julius Joseph Santillan, Toshiro Itani, Takeo Watanabe, Naohiro Matsuda, Tetsuo Harada, Hiroo Kinoshita

Proceedings Volume 7969, 796921 (2011) https://doi.org/10.1117/12.878571

KEYWORDS: Contamination, Extreme ultraviolet, Extreme ultraviolet lithography, Mirrors, Spectroscopy, Photography, Statistical analysis, Protactinium, Optical components, Line width roughness

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Proceedings Article | 26 March 2010 Paper

Development of EUV resists based on various new materials

Hiroaki Oizumi, Kazuyuki Matsumaro, Julius Santillan, Gousuke Shiraishi, Koji Kaneyama, Kentaro Matsunaga, Toshiro Itani

Proceedings Volume 7639, 76390R (2010) https://doi.org/10.1117/12.846429

KEYWORDS: Fullerenes, Extreme ultraviolet lithography, Line width roughness, Extreme ultraviolet, Lithography, Semiconductors, Manufacturing, Photoresist processing, Scanning electron microscopy, Etching

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Proceedings Article | 23 March 2010 Paper

Evaluations of EUV resist outgassing by gas chromatography mass spectrometry (GC-MS)

Hiroaki Oizumi, Kazuyuki Matsumaro, Julius Santillan, Toshiro Itani

Proceedings Volume 7636, 76362W (2010) https://doi.org/10.1117/12.846269

KEYWORDS: Extreme ultraviolet, Mass spectrometry, Calibration, Chromatography, Extreme ultraviolet lithography, Ions, Ionization, Chemical analysis, Semiconducting wafers, Molecules

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Proceedings Article | 20 March 2010 Paper

Development of resist material and process for hp-2x-nm devices using EUV lithography

Kentaro Matsunaga, Hiroaki Oizumi, Koji Kaneyama, Gousuke Shiraishi, Kazuyuki Matsumaro, Julius Joseph Santillan, Toshiro Itani

Proceedings Volume 7636, 76360S (2010) https://doi.org/10.1117/12.846088

KEYWORDS: Extreme ultraviolet lithography, Lithography, Photoresist processing, Line width roughness, Extreme ultraviolet, Manufacturing, Materials processing, Semiconductors, Analytical research, Semiconducting wafers

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Proceedings Article | 1 April 2009 Paper

Characterization of film cut position at wafer bevel for effective immersion lithography process

Kazuyuki Matsumaro, Miyoshi Seki, Takeshi Kato

Proceedings Volume 7273, 727325 (2009) https://doi.org/10.1117/12.813376

KEYWORDS: Semiconducting wafers, Inspection, Coating, Immersion lithography, Control systems, Sensors, Photoresist processing, Materials processing, Particles, Wafer inspection

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Proceedings Article | 24 March 2006 Paper

Tri-layer resists process for fabricating 45-nm L&S patterns by EPL

Fumihiro Koba, Kazuyuki Matsumaro, Eiichi Soda, Tadayoshi Watanabe, Yoshihisa Matsubara, Hiroshi Arimoto, Tasuku Matsumiya, Daisuke Kawana, Naoki Yamashita, Yasushi Fujii, Katsumi Ohmori, Mitsuru Sato, Takahiro Kozawa, Seiichi Tagawa

Proceedings Volume 6151, 615127 (2006) https://doi.org/10.1117/12.655976

KEYWORDS: Photoresist processing, Failure analysis, Etching, Back end of line, Semiconducting wafers, Critical dimension metrology, Electron beam lithography, Lithography, Extreme ultraviolet lithography, Photomasks

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In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.

Showing 5 of 6 publications

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