Due to the promising development status of EUVL as a practical lithography technology for the 2x-nm node, we are
continuing to evaluate its process liability using the EUV1 at Selete, which has an Off-Axis illumination capability. The
resolution limit of the EUV1 for L&S patterns is currently 18 nm for dipole illumination, and 16 nm for aggressive
dipole illumination. This study examined the critical points of EUVL for device manufacturing through wafer processes.
The yield obtained from electrical measurements indicates the maturity of the technology, including the resist process,
the tool, and the mask. Optimization of the resist and RIE processes significantly improved the yield. The final yields
obtained from electrical measurements were 100% for hp 30 nm, 70% for hp 28 nm, and 40% for hp 26 nm. These
results demonstrate EUV lithography to be a practical technology that is now suitable for 2x nm semiconductor
manufacture.
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
advanced optics.
A high-resolution EUV exposure tool is needed to facilitate the development of EUV resists and masks. Since the
EUV small-field exposure tool (SFET) has a high numerical aperture (NA = 0.3), low aberration & flare, and excellent
stage stability, it should be able to resolve fine L/S patterns for the half-pitch 22-nm & 16-nm nodes. In this study, we
evaluated the resolution capability of the SFET and obtained 22-nm L/S patterns with x-slit illumination and clear
modulation of 16-nm L/S patterns with x-dipole illumination. The resolution limit of the SFET seems to be about 15 nm.
The main cause of pattern degradation in 16-nm L/S is probably resist blur. To obtain good shapes for this pattern size,
the resist blur of less than 3.5 nm (σ) is required. The use of y-slit illumination was found to reduce the linewidth
roughness (LWR) of resist patterns. Further reduction of the LWR requires a higher image contrast and a smaller flare.
Due to the central obscuration, the image contrast of the SFET is sensitive to the change of pupil fill. The degradation in
the collector & DMT should be reduced to ensure stable aerial images. This work was supported in part by NEDO.
When a thinner absorber mask is applied to extreme ultraviolet (EUV) lithography for chip production, it becomes essential to a introduce light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. In this paper, we evaluate the leakage of both EUV and out-of-band from light-shield border and clarify the dependence of lithographic performance on light-shield border structure using a small field exposure tool with/without spectral purify filter (SPF). Then we evaluate the lithographic performance of a thin absorber EUV mask with light-shield border of the etched multilayer type and demonstrate the merit of its structure using a full-field scanner operating under the currently employed condition of EUV source in which SPF is not installed.
The key challenge before EUVL is to make defect-free masks, for which it is important to identify the root cause of
defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete
has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength
patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on
wafer printing. In this paper, by evaluating the printability of programmed phase defects and absorber defects exposed
by full-field scanner EUV1, we demonstrate that defect detection sensitivities of ABI (actinic blank inspection) and PI
(patterned mask inspection) are higher than that of WI (wafer inspection) in HP32nm. The evaluations were done by
comparing the detection sensitivities of full-field actinic blank inspection tool, 199nm wavelength patterned mask
inspection tool, and wafer EB inspection tool. And then, based on the native defect analysis of blank/mask, we
ascertained that actinic blank inspection and patterned mask inspection developed at Selete, are effective in detecting
killer defects both at the main pattern and at light-shield border area.
The key challenge before EUVL is to make defect-free masks hence it is important to identify the root cause of
defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete
has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength
patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on
wafer printing.
In this paper, we evaluate the printability of multilayer defects and of absorber defects exposed by a full-field scanner
EUV1, using full-field actinic/non-actinic blank inspection tool and 199nm wavelength patterned mask inspection tool.
And based on the results of native defect analysis of blank/mask, we ascertain that blank inspection with actinic is
necessary for mask fabrication in order to reduce the risk of missing phase defects, which hardly can be detected by
patterned mask inspection tool.
When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV
light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask
with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this
paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched
multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
The Selete full-field EUV exposure tool, EUV1, manufactured by Nikon, is being set up at Selete. Its lithographic performance was evaluated in exposure experiments with a static slit using line-and-space (L&S) patterns, Selete Standard Resist 03 (SSR3), a numerical aperture of 0.25, and conventional illumination (=0.8). The results show that 25-nm L&S patterns were resolved. Dynamic exposure experiments demonstrate that the resolution is 45 nm across the exposure field. The CD uniformity across a shot is 3 nm. Evaluation of the overlay performance of the EUV1 using alignment marks on a processed wafer revealed the repeatability to be better than 1 nm. The overlay accuracy obtained with enhanced global alignment was less than 4 nm (3) after linear correction. These results show that the EUV1 has attained the quality level of a typical alpha-level lithography tool and is suitable for test site verification.
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
Since the k1 factor is much larger in extreme-ultraviolet lithography (EUVL) than in optical lithography, optical
proximity correction (OPC) should be much simpler for patterns on EUVL masks than for those on advanced
photomasks. This will facilitate the fabrication of complex device patterns with EUVL. In this study, static
random-access memory (SRAM) cell patterns for the half-pitch (hp) 32- and 45-nm nodes were fabricated using two
EUV exposure tools (SFET, EUV1), and their fidelity was evaluated. The levels of SRAM patterns were isolation, gate,
contact, and metal. The size of the SRAM unit cell was 0.191 μm2 for the hp 45-nm and 0.097 μm2 for the hp 32-nm
patterns. Most of the experiments employed SSR2, a high-resolution EUV resist. The high performance of the SFET and
SSR2 enabled hp 45-nm SRAM patterns to be fabricated faithfully. However, some of the hp 32-nm patterns deviated
from the mask patterns. To determine the causes of this degradation, we made a simulation analysis using the Sentaurus
Lithography simulator. The main cause of the degradation was found to be resist blur. When we used MET-2D resist,
which has a relatively large resist blur, the degradation became quite severe. Although the resist blur for SSR2 is about
10 nm, it is not small enough for the hp 32-nm SRAM patterns, especially for the gate and metal levels. It is necessary to
reduce resist blur to improve the fidelity for this pattern size. Simulation results indicated that resist blur should be
reduced to about 5 nm for hp 22-nm node device patterns.
The source collector module (SoCoMo) for the extreme ultraviolet (EUV) small-field exposure tool (SFET) had been
operated for 1,700,000,000 pulse radiations using more than 20 electrodes, four debris mitigation tools (DMT), and three
collector mirrors. After 600 million pulse radiations, it was found that the EUV light intensity at wafer plane had been
decreased to less than 10% of the initial value and the pupilgram exposed by SFET had been drastically deteriorated. In
order to study on the cause of the intensity reduction and to maintain the intensity highly, three new evaluation tools
were introduced; collector position monitors, an intermediate focus (IF) spot position monitor, and an attachment of
screen tool. Utilizing these tools, it was clarified that the main causes of EUV light intensity reduction at IF plane were
the plasma fluctuation with electrode erosion, the degradation of DMT's optical transmissivity, and the degradation of
collection efficiency. These results indicated that it would be necessary for future SoCoMo not only to achieve highpower,
stable and long-life performance, but also to equip with the functions that these tools provided in order to
maximize its own performance.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
The Selete full-field EUV exposure tool, the EUV1, was manufactured by Nikon and is being set up at Selete. Its
lithographic performance was evaluated in exposure experiments with a static slit using line-&-space (L&S) patterns,
Selete Standard Resist 03 (SSR3), an NA of 0.25, and conventional illumination (σ = 0.8). The results showed that 25-
nm L&S patterns were resolved. Dynamic exposure experiments showed the resolution to be 45 nm across the exposure
field and the CD uniformity across a shot to be 3 nm, also 26-nm L&S patterns were resolved.
Overlay performance of the EUV1 was showed as processed wafer mark alignment, the repeatability was under 1nm.
Overlay accuracy using EGA (Enhanced Global Alignment) was below 4nm at the 3-sigma after liner correction. These
results were good enough for an alpha-level lithography tool and test site verification.
We have installed a small-field exposure tool (SFET) manufactured by Canon and EUVA with a discharge-producedplasma
EUV source that employs Xenon gas. We investigated how the performance of the source affects lithographic
performance. Electrode life has relation to the illumination uniformity of the exposure field on wafer surface. Also
source power at the wafer surface has relation to the electrode life. Electrode life makes EUV power decreasing and
larger illumination uniformity number. We examine the pupilgram test using high sensitivity resist. Actual pupil fill
shape was observed and there was non-uniform distribution. Pupil fill shape was changed after exchanging electrode,
also resist CD bias between parallel and horizontal line of the field. That was comparable to the simulation result.
The source electrode requires periodic replacement, which impacts not only the performance of the source, but also the
lithographic performance of the tool, such as the CD of resist patterns.
The effects of aberration and flare on the lithographic performance of the EUV small-field exposure tool (SFET)
were evaluated. Simulation results indicated that the effect of aberration on the image contrast of line-and-space (L&S)
patterns should be small. In exposure experiments, 26-45-nm L&S patterns were successfully fabricated under annular
illumination (σ=0.3/0.7). A key factor limiting resolution should be resist performance. Simulation results also indicated
that the astigmatic aberration could produce a focal shift of about 60 nm between horizontal and vertical L&S patterns.
The experimentally obtained focus shift agreed well with the simulation results. Dense 32-45-nm contact-hole (C/H)
patterns were also successfully fabricated under annular illumination (σ=0.3/0.5). Due to astigmatic aberration, the C/H
patterns were deformed at defocused positions, but they were almost circular at the best focus position. The flare of the
projection optics measured by the Kirk method was 11% over a flare range of 1-100 μm. The effects of the 11% flare
were evaluated using dark- and bright-field 32-nm L&S patterns. It was found that the top loss and line-width roughness
(LWR) of the resist were larger for bright-field than for dark-field patterns. To reduce the impact of flare, we need EUV
resists that are more robust with regard to flare. A comparison of the measured point spread function (PSF) of the flare
and the calculated PSF revealed good agreement for long-range flare but some difference for short-range flare.
KEYWORDS: Semiconducting wafers, Metals, Backscatter, Electron beam lithography, Copper, Lithography, Electron beam direct write lithography, Monte Carlo methods, Critical dimension metrology, Tungsten
Direct write electron-beam (e-beam) lithography, which has the maskless patterning capability and the quick turnaround for new device designs and design changes, has been applied to making the engineering samples for the development of the System on Chip products (SoC). Using the e-beam lithography to the multilevel interconnect metal was known to be evaluate in view of cost and throughput. In the case of the high-energy e-beam lithography, however, the backscattered electron from the metal caused a significant proximity effect.
Authors evaluated the e-beam proximity effect using the accelerating voltage 50keV on some multi-level interconnect metal structures which consist in tungsten wiring, or Cu wiring. It was found that the backscattering range and the ratio of the backscattering energy to the incident energy depend on the thickness of metal, but also on the distance from the resist to the metal.
Therefore authors propose a new method of evaluating e-beam lithography property, concept of "EB-tree". That indicates the wafer backscatter property that has heavy metal wiring using e-beam lithography. EB-tree shows the relations of wafer backscatter range and heavy metal thickness, ratio of the backscattering energy and heavy metal thickness. EB-tree could show wafer property cause of lower levels layout, understructure metal wiring, that must be taken into account when e-beam lithography.
Recently, the critical dimension (CD) abnormality due to lens aberrations of exposure tool has become one of the critical issues in production of semiconductor devices. The most remarkable feature of CD abnormality due to lens aberration is asymmetry of symmetric twin pattern. And the asymmetry is only caused by a particular aberration because the influence on CD abnormality of lens aberration depends on the device pattern shape. Therefore, it is important to know the interaction of the device pattern shape with lens aberrations, and to ensure that consideration of the interaction is reflected in the design of device. This paper introduces a pattern design methods robust to lens aberration is based on Zernike Sensitivity (ZS) method. We conclude that our method modifies a pattern sensitive to lens aberration so that it becomes a pattern robust to lens aberration without reduction of the depth of focus (DOF).
In the application of the high-energy electron-beam (e-beam) lithogrpahy to the multi-level interconnect metal; the backscattered electron from the heavy metal previously patterned in lower levels on the substrate causes a significant proximity effect. We estimated the "inter-level" proximity effect in the e-beam exposure with the accelerating voltage of 50kV on some multi-level interconnect metal structures which consist in aluminum wiring and tungsten plugs. It was found that the backscattering range and the backscattering energy ratio to the incident energy depend not only on the density and thickness of metal but also on the distance between the resist and the heavy metal plugs. In this paper, a novel proximity effect correction algorithm is proposed, where the exposing patterns are divided into some classes according to the metal structure, the total backscattering energy deposited in the resist is expressed by the sum of the backscattering energy from each structural class, and the exposrue dose is modulated by the function of the total backscattering energy.
Measurement techniques for higher order aberrations of a projection optical system in photolithographic exposure tools have been established. Even-type and odd-type aberrations are independently obtained from printed grouped lines on a wafer by three-beam interference under highly coherent illumination. Even-type aberrations, i.e. spherical aberration and astigmatism, are derived from the best focus position of vertical, horizontal and orthogonal grouped lines by an optical microscope. Odd-type aberrations, i.e. coma and trefoil, are obtained by detecting relative shifts of fine grouped lines to a large pattern by an overlay inspection tool. The qualitative diagnosis for lens aberrations was demonstrated to a krypton fluoride excimer laser scanner.
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