The correlation between the amount and rate of etching and various properties of organic film for multi-layer resist
(MLR) was investigated. The etching critical dimension (CD) of 140-nm pitch interconnects is controlled by the etching
conditions as well as by the properties of the organic film used as the bottom layer resist. Six organic films were tested
that had different densities, hardness values, refractive indexes, and FT-IR peaks. Patterned samples of these films were
exposed using electron projection lithography. The results showed amount of side etching, which effects the etching CD
of interconnects, of the bottom layer depended on the etching rate of the film. In turn, the etching rate depended on a
film's hardness and refractive index, but not on its density. The etching rate decreased with increasing hardness and with
increasing refractive index in the visible wavelength spectrum. Consequently, the etching CD of interconnects can be
better controlled by using an organic film as the bottom layer resist when the film has appropriate properties.
In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.
Electron Projection Lithography (EPL) provides a fundamental advantage in resolution. In this paper, resolution improvement of EPL masks and minimum resolution in EPL exposure are addressed. In order to improve the mask resolution, we applied membranes thinner than typical thickness of 2 um to e-beam scattering layers of the EPL stencil masks. Although strength of the membrane generally deteriorates with decrease in the membrane thickness, the EPL masks having 1-um-thick scattering layers were feasibly fabricated. Reduction of the membrane thickness down to 1 um considerably improved the mask minimum feature size to resolve 120-nm holes and 80-nm lines which corresponded to 30 nm and 20 nm on wafer dimension, respectively, in the 4x demagnification EPL exposure system. The application of the 1-um-thick membrane simultaneously brought the high resolution and good pattern qualities: CD uniformity less than 10 nm in 3σ with pattern sidewall angle range of 90° ± 0.2°. We performed wafer exposure experiments in combination of the EPL exposure tool NSR-EB1A (Nikon) and the 1-um-thick membrane mask, and obtained the resolution performance of 40-nm holes on the wafer. We conclude that the application of the 1-um-thick membrane to the e-beam CD qualities. The exposure resolution of 40-nm holes on the wafer reveals the EPL exposure system to be a potential solution for contact layers in the future technology node.
KEYWORDS: Metals, Transmission electron microscopy, Lithography, Scanners, Copper, Scanning electron microscopy, Resistance, Electron beam lithography, Overlay metrology, Chemical mechanical planarization
We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.
Electron projection lithography (EPL) is a promising candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. Nikon has developed the world's first full-field EPL exposure tool, Nikon's NSR-EB1A. This tool was shipped to Selete in June 2003. Final installation is still in progress, but we have begun evaluating its applicability to the 65 nm technology node through trial fabrication of a test element group (TEG). A TEG of via-hole chains consisting of 1st metal, 1st via, and 2nd metal layers was fabricated using optical/EPL mix-and-match lithography.
We applied EPL to the via layer. The purpose of the first fabrication is to clarify practical hole resolution of the EPL tool because EPL is expected to define finer hole patterns and enable denser integration than optical lithography. To prevent defects in metal layers from adversely affecting evaluation, we used moderate pattern layouts in metal layers. Metal layers were defined by an ArF scanner to obtain good pattern fidelity and sufficient pattern yield. We used a single damascene process with a low-k insulator and Cu interconnection. Practical hole resolution was evaluated by electrical measurement and SEM and TEM observation. SEM confirmed that via holes of 70 nm were resolved. TEM confirmed that via-hole chains of 80 nm were fabricated. Electrical measurement confirmed electrical conduction through via-hole chains of 75 nm. These results suggest that applying EPL to hole layers could realize denser integration than optical lithography. EPL application to TEG trial fabrication demonstrates its high-resolution capability in practical use.
The world’s first electron projection lithography (EPL) R&D exposure tool was installed at our laboratory in June 2003, and we have evaluated its basic performance. The most feasible introduction of EPL into ultra-large-scale integration (ULSI) is mix-and-match use with an optical tool for critical layers at the 65 nm technology node (TN) and beyond. Overlay is the most crucial issue in mix-and-match lithography, so we focused on overlay in this evaluation. We found that the overlay performance of the EPL tool in mix-and-match use is 48.0 nm in the X direction and 45.7nm in the Y direction. To clarify details of deteriorated overlay accuracy, we divided it into 7 factors, finding underlayer distortion to be about 15 nm, residual reticle distortion 5 nm, subfield (SF) distortion 15 nm, main-field (MF) distortion 20 nm, reticle alignment accuracy 15 nm, repeatability 25 nm, and exposure field distortion 25 nm. We also demonstrated that overlay accuracy was 30 nm using previous overlay data.
Electron projection lithography (EPL) is a potential candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. EPL presents two key issues influencing design, because EPL uses EB and a stencil mask: beam blur and mask image placement (IP). Beam-blur deterioration depends on the Coulomb effect and is proportional to the beam current on the wafer, which depends on pattern density and the beam current on the mask. Pattern density in each subfield (SF) must be limited if the beam current on the mask is decided from throughput. IP accuracy of the stencil mask depends on the pattern layout. Intrinsic stress vanishes at openings, and distorted stress distribution causes IP error. To determine the influence of pattern layout on mask IP accuracy, simulation is checked in two steps. In the first step, simulation calculates the correlation between maximum displacement and pattern density in the entire SF. In the second step, simulation calculates the correlation between the side length of local area L and maximum additional displacement. The result of the first simulation shows that pattern deformation depends on the difference between half of the SF’s patterns density difference. To estimate the influence of pattern density imbalance in an area smaller than half of the SF, additional deformation of local area (L x L) is calculated in the second simulation step. Maximum additional displacement increases with L and pattern density. Based on the correlation between beam blur and pattern density and simulations results, the design rule (DR) for EPL is defined as the maximum pattern density in each entire SF and local area (L x L).
KEYWORDS: Quantum efficiency, Projection lithography, Lithography, Electron beam direct write lithography, Electron beam lithography, Electron beams, Photomasks, Scanning electron microscopy, Molecules, Chemical analysis
Electron beam (EB) lithography has often been used for fabricating advanced ULSIs. Recently, to increase the throughput, EB projection lithography (EPL) has been proposed. If 100 kV acceleration voltage and 20 to 30 (mu) A beam current are to be adopted in this technology, a high sensitivity resist will have to be developed to achieve a throughput of more than 30 wafers/hour (8'(phi) ). In this paper, we show the photoacid generator (PAG) optimization of a polyhydroxysterene (PHS)-based chemically amplified negative resist for EPL. To evaluate the resist sensitivity and the resolution, we prepared the PHS-based negative resists with PAGs of various quantum yields of acid generation, which were the onium-salt- type PAG, the imide-type PAG, and the alkylbenzene-type PAG. The cross-linker was the melamine-type one. Two simultaneously obtain a high sensitivity of less than 10.0 (mu) C/cm2 and a high resolution of less than 0.10 micrometer, a PHS-based negative resist with the imide-type PAG was most preferable. With this resist, we successfully obtained 0.08-micrometer gate line patterns (128 K sub-array of DRAM), exposed by one 250 X 250 micrometer2 EB shot using a 100-kV EB projection experimental column. In addition, the throughput was estimated to be 30 wafers/hour (8' (phi) ) or more.
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