This paper presents a system for performing mask error correction on both Manhattan and curvilinear shapes. On the Manhattan shapes, the correction may move segments (dissected edges), and on the curvilinear shapes, the correction may move vertices. The segment movement preserves the Manhattan style of the original shapes. Optionally, the vertex movement may be applied on the Manhattan shapes and the corrected results change to be in the curvilinear style. The results of mask error correction on the post-OPC mask of a logic layout will be reported. Dissection and target-point placement work differently between Manhattan and curvilinear shapes. We will analyze the quality and demonstrate optimization of the mask error correction strategies for input mask data consisting of both Manhattan and curvilinear shapes.
Through techniques such as ILT, curvilinear designs and their associated masks have demonstrated benefits over Manhattan type for delivering superior wafer lithography process latitude. Moreover, a number of native design applications such as silicon photonic IC and curvilinear interconnect require delivery of masks with non-Manhattan geometries. Consequently, as enabled by the use of multi-beam mask writers (MBMW), we see the adoption of curvilinear masks in production to grow steadily. One of the more challenging topics for curvilinear adoption is on determining the optimum tradeoff between mask manufacturability and wafer imaging. To maximize the benefits of curvilinear masks without incurring an undue impact from mask complexity, it is beneficial to develop optimized layout validation checks such as MRC which can be implemented to achieve an optimum tradeoff. We will present a methodology to perform curvilinear mask manufacturability optimization using a specially designed set of parametric curvilinear test patterns. The techniques are demonstrated in support of a DRAM implementation study where ILT is applied to improve the wafer performance of a contact type layer. We describe a parametric test chip covering curvature, width, space and area and the mask data generated is applied to evaluate different curvilinear layout constructs and correlations between mask manufacturability and simulated wafer performance. We revisit the question on whether ILT actually leads to relaxed MRC constraints compared to Manhattan designs for the same design application. In addition, advanced mask characterization techniques such as 2D contouring are applied to consider the limitations of purely geometrical rule checking versus a full model based approach that can consider mask pattern fidelity in ILT layout generation.
In prior work, as a means to overcome computational cost while maintaining similar ILT lithographic quality, we presented full-chip layout synthesis with curve-based OPC as a complimentary option with curvilinear ILT. However, there are an increasing number of different quality determinations, cost constraints and orthogonal solutions needed for curvilinear mask and target correction to meet the requirements for different layers (L/S, CH/Via/Cut-mask), devices (logic, DRAM, Flash) and lithographic applications (DUV, EUV, photonics, flat-panel display, High NA EUV), etc. In this paper, we will share a spectrum of advances for curvilinear masks and targets by ILT, and integrated curve-based ILT/OPC. These varied solutions can achieve the quality and computational cost requirements for the different application areas previously listed. Additionally, we will also describe new advancements in adjacent areas of the curvilinear mask ecosystem for MRC, MEC, etch and data volume reduction.
With recent technology advancements of multi-beam mask writers, curvilinear masks can now be extended to advanced EUV lithography generations. Inverse lithography technology (ILT) is a curvilinear mask-friendly mask synthesis solution with superior quality but slower TAT than mainstream rule-based assist feature + OPC methods. To achieve ILT quality for full-chip layouts, a faster curvilinear ILT-based mask synthesis solution is desired. We present a hybrid curvilinear mask solution with ILT and curve OPC for full-chip EUV layers. Results of full-chip EUV in lithographic performance and runtime are compared among different solutions including traditional Manhattan OPC, curvilinear ILT, and hybrid machine learning (ML) ILT plus curve OPC. Another important factor of curvilinear mask advancement is data volume. We present our curve OPC solution with the cubic Bezier curve to control the data volume of curvilinear masks. The mask writing process is playing an increasingly important role in the overall manufacturing flow. Therefore, we also present an enhanced mask synthesis flow utilizing a mask error correction solution for curvilinear masks written by a multi-beam writer.
The edge-based optical proximity correction (OPC) has been serving the industry for more than 20 years with few changes the mask geometry. In the past 10 years, ILT pioneers created the curvilinear mask using alternate algorithms. The two approaches differ so much that the experiences in conventional OPC do not easily translate to the use of ILT, and vice versa. We report a new approach to curvilinear masks that follows the conventional OPC workflow. It creates and manipulates the curvilinear shapes by generalizing the edge-based OPC to vertices. Conventional OPC techniques, including dissection, classification, target point placement, etc., remain as central roles. Full-chip correction results are included to demonstrate the good performance of the curvilinear mask for both contact and line/space patterns. The analysis of critical patterns shows that the curvilinear OPC lifts the mask rule check restriction to the mask shape that limits Manhattan OPC. The turnaround time of creating the curvilinear mask is around two times than that of the Manhattan mask.
The edge-based OPC has been serving the industry for more than 20 years with few changes in the way to alter the mask. In the past 10 years, ILT pioneers in the creation of the curvilinear mask using alternate algorithms. The two approaches differ so much that the experiences in conventional OPC do not easily translate to the use of ILT and vice versa. In this paper, we report a new system for curvilinear OPC built on top of the conventional OPC workflow without being limited to moving edges. It creates and manipulates the curvilinear shapes by generalizing the edge-based OPC to vertices. Conventional OPC techniques, including dissection, classification, target point placement, etc., keep playing central roles. Full-chip correction results demonstrate the good performance of the curvilinear mask for both contact and line/space patterns. The runtime cost of adoption is reported.
With the emergence of complex ILT (Inverse Lithography Technology) and multi-beam mask writers, comes the rise of curvilinear masks. Curvy shapes or all angle piecewise linear polygons provide optimal results for chip makers as it provides larger process windows. For mask manufacturers, the objective remains the same; writing a mask that meets the chip makers’ specifications. However, if the curvilinear shapes need biasing to correct for process effects, then individual edge adjustment is not an appropriate solution as the segment lengths are extremely small. This approach would require far more computational resources then it would for the typical Manhattanized layout. Thus, as the industry transitions from traditional layouts with rectilinear polygons to full curvy, or even a hybrid mix, there must be an optimized path available that enables a more ‘holistic’ approach to correction for all types. One that can balance ease-of-use, data complexity, and robust enough to meet strict tolerances and EPE specifications. In this paper, we will outline a fully supported MDP flow for curvilinear masks. The functionality is provided by the Proteus Curvilinear OPC engine and fully supports ILT and EUV layers as well as other curvilinear masks. We will provide an overview of the data path, from correction to multi-beam writer format. We will also describe the controls necessary to achieve optimal quality and share both data metrics and performance results.
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