Through techniques such as ILT, curvilinear designs and their associated masks have demonstrated benefits over Manhattan type for delivering superior wafer lithography process latitude. Moreover, a number of native design applications such as silicon photonic IC and curvilinear interconnect require delivery of masks with non-Manhattan geometries. Consequently, as enabled by the use of multi-beam mask writers (MBMW), we see the adoption of curvilinear masks in production to grow steadily. One of the more challenging topics for curvilinear adoption is on determining the optimum tradeoff between mask manufacturability and wafer imaging. To maximize the benefits of curvilinear masks without incurring an undue impact from mask complexity, it is beneficial to develop optimized layout validation checks such as MRC which can be implemented to achieve an optimum tradeoff. We will present a methodology to perform curvilinear mask manufacturability optimization using a specially designed set of parametric curvilinear test patterns. The techniques are demonstrated in support of a DRAM implementation study where ILT is applied to improve the wafer performance of a contact type layer. We describe a parametric test chip covering curvature, width, space and area and the mask data generated is applied to evaluate different curvilinear layout constructs and correlations between mask manufacturability and simulated wafer performance. We revisit the question on whether ILT actually leads to relaxed MRC constraints compared to Manhattan designs for the same design application. In addition, advanced mask characterization techniques such as 2D contouring are applied to consider the limitations of purely geometrical rule checking versus a full model based approach that can consider mask pattern fidelity in ILT layout generation.
The edge-based optical proximity correction (OPC) has been serving the industry for more than 20 years with few changes the mask geometry. In the past 10 years, ILT pioneers created the curvilinear mask using alternate algorithms. The two approaches differ so much that the experiences in conventional OPC do not easily translate to the use of ILT, and vice versa. We report a new approach to curvilinear masks that follows the conventional OPC workflow. It creates and manipulates the curvilinear shapes by generalizing the edge-based OPC to vertices. Conventional OPC techniques, including dissection, classification, target point placement, etc., remain as central roles. Full-chip correction results are included to demonstrate the good performance of the curvilinear mask for both contact and line/space patterns. The analysis of critical patterns shows that the curvilinear OPC lifts the mask rule check restriction to the mask shape that limits Manhattan OPC. The turnaround time of creating the curvilinear mask is around two times than that of the Manhattan mask.
The edge-based OPC has been serving the industry for more than 20 years with few changes in the way to alter the mask. In the past 10 years, ILT pioneers in the creation of the curvilinear mask using alternate algorithms. The two approaches differ so much that the experiences in conventional OPC do not easily translate to the use of ILT and vice versa. In this paper, we report a new system for curvilinear OPC built on top of the conventional OPC workflow without being limited to moving edges. It creates and manipulates the curvilinear shapes by generalizing the edge-based OPC to vertices. Conventional OPC techniques, including dissection, classification, target point placement, etc., keep playing central roles. Full-chip correction results demonstrate the good performance of the curvilinear mask for both contact and line/space patterns. The runtime cost of adoption is reported.
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