Semiconductor wafer fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The BEOL processes include dielectric film deposition, patterning, metal fill and planarization by chemical mechanical polishing. The state-of-the-art semiconductor chips, the so called 5 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features the fifth generation three-dimensional (3D) FinFET, a minimum metal pitch of about 28 nm and copper (Cu)/low-k interconnects. It is the second generation of logic chips fabricated with extreme ultra-violet (EUV) lithography. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor wafer fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers with a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high mobility channel materials, high-K/metal gate or HKMG, III-V materials, non-copper BEOL metals), new device and interconnect structures (such as, gate-all-around transistor, FinFET/ Trigate, nanowires, self-aligned via integration, Cu/air-gap interconnects, buried power rails, PowerVia) and new integrations (such as 3D IC, Through-Silicon Via or TSV, 3D heterogeneous integration, hybrid bonding) as well as recent advances in lithography technology (such as double patterning, EUV lithography, high-NA EUV and directed self-assembly, DSA). Implications of these FEOL, MOL and BEOL technologies for lithography will be discussed.

Semiconductor Back-End-Of-The-Line (BEOL) or interconnect constitutes the bulk of the film stack and the fabrication cost of modern computer chips. The state-of-the-art BEOL features Cu/low-<i>k</i> interconnects with a dielectric constant (<i>k</i>) of the low-<i>k</i> material of less than 3.0. These Cu/low-<i>k</i> interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs) and PVD Cu barrier materials. Successful fabrication and qualification of modern semiconductor BEOL requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor BEOL, its integration schemes and fabrication processes. It highlights unique challenges in lithography for BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials and lithography engineers a fundamental basis to develop materials and processes for BEOL patterning and to trouble shoot BEOL fabrication problems.