Aggressive off-axis illumination must be used to resolve line space pitches of 28nm and below. The consequence is that the best focus (BF) shifts a lot and depth of focus shrinks rapidly through pitch. This is mainly due to the mask 3D effects. To reduce the impact the best-known method is to introduce sub-resolution assist features (SRAF). We explored wafer printing with SARF size of 6-8 nm and analyzed BF and DOF impact. Clear SRAF sizes of 6-8 nm do not print with PCAR but some 7-8 nm clear SRAF printed with NTD MOR due to the higher resolution and over exposure preference. Then we validated the experiments with SLITHO simulation tool, and we found a good experiment-simulation match of BF/DOF/EL/MEF w and w/o SRAF through pitch with the three P28 illumination candidates. Overall SRAF can improve the DOF and exposure latitude (EL) for the given pitches with SRAF capable and help shift the BF to the favored focus direction. With the validated model we further study BF/DOF/EL/MEF w and w/o SRAF through pitch with the small/medium/large sigma illuminations designed for 28nm pitch, with traditional TaBN and other three candidate absorbers. We will also discuss the SRAF size and placement sensitivities. Through this work we are confident to implement SRAF to enlarge the common process window for a large range of pitches.
In photolithography, we need accurate models as computation engine for optical proximity correction (OPC). Traditional OPC modeling consists of a series of components for photo mask, optical exposure system, and resist materials. These models are trained using compact model forms based on wafer-level critical dimension (CD) or edge placement error (EPE) measurements. In recent years, advancements in neural networks and machine learning have had significant advancements. In this work, we evaluated advanced neural network-based resist models on a Tensor Flow machine learning platform. This work describes resist and optical response of machine learning (ML) model through process window to achieve improved model representation of lithography process. Using ML OPC vias mask as an example, we will show improved accuracy through dose and focus process conditions and verify model accuracy with physical hardware data. Also, we will compare multiple neural network-based modeling approaches, investigate the ML models’ impacts on OPC correction and verification recipes, and dataprep runtime. The machine learning based OPC with ML model and best practice will be implemented in cloud production environment.
Background: In EUV lithography, the absorber material determines the amplitude and phase of the diffracted orders, which define best focus (BF) and depth of focus (DOF). Control of BF and DOF is needed for mid and high numerical aperture (NA) systems. Aim: Generate recommendations for EUV absorber classes and explain the best focus shifts that occur for bright and dark field mask imaging. Approach: We anchor simulations with experiments using a TaBN absorber, then investigate the BF and DOF for various absorbers using simulation. We use a simple analytical model to show that the analytically predicted diffraction orders behave similarly in magnitude and phase to EMF simulations. Results: We find good prediction for BF experiments and simulations using a very simple resist model, and fair prediction in DOF. We explain the BF shift depending on simple absorber parameters using an analytical model. The exact BF shift needs to be calculated using EMF simulations. Conclusions: Best focus shifts are more pronounced for dark than clear field masks, and more so in attPSM materials than in more binary absorbers. Magnitude and phase of the 0th order plays an important role in BF shifts. We are encouraged to explore low-reflection attPSM materials as mask absorbers.
Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.
The imaging of an immersion lithography system has different sensitivities to optical errors such as reticle non-flatness,
image plane deviation and laser bandwidth when compared to traditional dry imaging systems. The immersion
sensitivities mentioned above are further amplified when higher fluid index is used. The resultant effect of these
enhanced sensitivities leads to degraded focal plane flatness centering on wafers and may also lead to larger ACLV and
machine to machine CD matching errors than expected. In this paper, we demonstrate the increased sensitivity factors
both mathematically and experimentally. We perform a detailed error component analysis to single out an immersion
related factor and its impact to CD control. For this purpose we independently quantify the reticle non-flatness directly
on the mask. We also identify possible compensation solutions, such as reticle shape correction, improved focal plane
setup methodology and the incorporation of focus blur into an OPC model, in order to alleviate an adverse effect of
immersion on ACLV and CD stability over time and over different tool sets.
Immersion lithography has emerged as the leading solution for semiconductor manufacturing for the 45nm node. With the emergence of the first full-field immersion lithography scanners, the technology is getting ready to be inserted in semiconductor manufacturing facilities throughout the world. In the initial implementation phase, the enhanced depth-of-focus provided by immersion will be utilized to mitigate the narrow process window in which leading-edge semiconductor manufacturing has been forced to operate, creating a new set of opportunities.1 The area of defects, however, has remained of critical concern for this technology. It has become clear that the ultimate proof of the readiness of immersion, especially from a defect point of view, must be attained by integrating the immersion process in a production environment. In this paper, we demonstrate that fully functional 90nm PowerPCTM microprocessors have been fabricated using immersion lithography for one of the litho-critical via levels, achieving the goal of confirming that immersion lithography is a viable manufacturing solution. For this demonstration, we utilized the AT1150i (ASML), currently at Albany NanoTech (NY). The system is a 0.75 NA full-field 193nm projection (4x) scanner. We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules. We have classified the leading types of defects that can be attributed to the immersion process and have assessed their processing impact. Electrical characterization of the integrated devices confirmed full functionality at both wafer final test (WFT) and module test (MT).
Anomalous linewidth variations of tens of nanometers have been observed for certain chemically amplified resist processes, a phenomenon we call chemical flare. These variations are highly undesirable, since they fall outside the scope of normal OPC corrective action. Experimental data is presented which clarifies the magnitude and range of chemical flare for two different 193nm resist processes. We observed that very weak background exposure, less than half the dose required to clear the resist, can have profound effects when chemical flare is strong. A TARC coating was found to completely eliminate chemical flare. In the absence of a first principles understanding of this phenomenon, we demonstrate simple screening tests for assessing resist processes.
Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 nm dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.
The problem of image shortening is well known in semiconductor lithography. As rectangular features decrease in width, the length of the feature will print smaller than the mask image length. This problem places a constraint upon overall device design because space must be allowed for line extensions and/or adding to the side of features. Making corrections for image shortening requires mask redesign, which increases the time and cost of new product development.
Defect repair is a key component in fabricating a defect- free mask. Focused ion beam repair has been successfully used for x-ray masks. To repair an opaque defect the ion beam is used to mill away the excess absorber while clear defect repair requires beam assisted deposition of Au. Current x-ray mask repair tools specify edge placement accuracy of +/- 25 mask nm. However, the effects of non- ideal repairs on printed resist have not been investigated, and the tolerance of such errors have not been specified. In this study, reported defect printing was tracked and resists edge placement accuracy was measured to evaluate the non- ideal repair effects. In the opaque defect repair case, we observed inside the 'repair box', repaired mask errors such as sloped walls, remaining absorber and re-deposition outside the box and found that these errors shift the printed resist pattern edge toward the inside of the box. In the clear defect repair case, the deposited gold is typically extended out of the defined box by sloped side- wall and the printed resist pattern edge is shifted toward the outside of the box. These non-ideal repairs systematically affect resist pattern edge placement. An x- ray lithography simulation tool was used to analyze these effects. Preliminary by adjusting the 'repair box' size and etch/deposition time, the effects of non-ideal repair can be eliminated. Programmed defects were created on a mask and repairs were performed, evaluated and optimized with actual x-ray exposures.
The development of the future-generation magnetic recording heads is based on availability of high resolution and high- aspect ratio lithography. A key step in the magnetic head fabrication process is the formation of high-aspect ratio trenches in photoresist that are subsequently used as a plating mask for the magnetic read-write heads. Currently, 1.2 to 1.5 micrometer wide and 10 micrometer tall trenches in the resist are formed using optical lithography. In the near future, more than 6 micrometer tall resist patterns with trenches of 0.5 micrometer or smaller will be required. A study of using X-ray lithography to generate patterns suitable for future-generation magnetic recording heads was undertaken at the Center for X-ray Lithography at UW-Madison. It was successfully demonstrated that 0.8 micrometer trenches in 15 micrometer thick resist and 0.4 micrometer trenches in 6 micrometer thick resist can be formed. The main steps in the fabrication of the high-aspect ratio resist patterns included (1) production of an initial (master) mask using e-beam lithography, (2) high-contrast replicated (final) X-ray mask manufacturing using X-ray replication process, and (3) actual patterning of thick PMMA resist using the final masks. Both X- ray masks were formed on a 2 micrometer thick silicon-nitride membranes as mask carrier. APEX-E resist 0.5 micrometer thick was used for e-beam writing, and 2 micrometer thick PMMA was utilized for the replicated mask. The absorber was electroplated gold: 0.4 micrometer thick for the master and 1.5 micrometer thick for the final mask. Details are given for 6 micrometer and 15 micrometer thick crack-free PMMA resist formation and characterization, exposure and development conditions.
The process for replication of high aspect ratio Au patterns typically includes x-ray lithography, RIE and electroplating. In this paper study of linewidth of dense L/S patterns in a wide range of periods is undertaken through the replication process. Effects of exposure dose, mask-wafer gap, RIE and electroplating process parameters on linewidth are addressed. We found that RIE parameters are the main factor affecting the linewidth. Based on the result of this study, we propose to introduce a bias in the mask pattern to the linewidth. Based on the results of this study, we propose to introduce a bias in the mask pattern to compensate the linewidth changes occurring during subsequent replication steps. Most interestingly, a mask with a required bias can also be produced by a self-biased process. Bias adjustment has been demonstrated for 0.1/0.1 micrometers L/S features with aspect ratio of 6. To further increase aspect ratio, a wet process is developed. An aspect ratio of 9 is achieved for 0.1 micrometers Au L/S patterns by using the wet process. With this method, the linewidth fidelity during replication is substantially improved.
In this work we characterized (1) the resist stress dependence on exposure dose and (2) in-plane distortions of the mask caused by resist and substrate. A NIST standard ring with a SiN membrane window as used throughout this work. Resist stress was determined by measuring the resonant frequency of membrane coated with resist. Stress was measured at several doses for SAL605, APEX-E and PMMA resists. In-plane distortion was measured using in-situ measurement approach. An array of standard alignment fiducials for Leica-Cambridge EBMF10.5 e-beam system were placed directly on the membrane. Also, an array of fiducials was placed on the NIST ring to provide a reference point for measurements. The position of the fiducials on the membrane was measured before and after exposure, and compared to position of a common reference point. The magnitude of displacements agreed with theoretical values for measured stress coefficients. The accuracy and limitations of the methods used to obtain the distortion data, as well as possible strategies for reducing the in-plane distortions are also discussed here.
In this paper we report the results of simulations and experiments on application of phase-shifting mask to x-ray lithography (XPM). We have built an XPM with PMMA as a phase shifter; we printed patterns using the XPM and characterized the linewidth dependence on gap and dose. Small lines around 70 nm were printed at 25 micrometer gap. The resist lines have good uniformity, and aspect ratio as high as 4. The characterization experiment was performed on the Karl Suss X- ray Stepper installed at the Center for X-ray Lithography. The results show that the exposure-gap latitude window is obviously increased compared with traditional x-ray mask. XLITH has been used to analyze the aerial image under the XPM and predict linewidth. Different phase shift materials, such as PMMA, Si, SiC and Al have been simulated and characterized with respect to blur, dose and gap. The model predicts a mask contrast 6 - 7, and resolution of 50 nm using gaps around 5 micrometer. XPM is a path to nanostructures with more reasonable process latitudes. We printed sub-0.1 micrometer dots using XPM. The XPM can also be used for gate-level lithography of ultrafast MOS devices to share its high resolution and large process latitude. It is possible to form both of a fine gate line and a contact pad at the same time with the combination of phase and transmission in a single mask. An experimental demonstration of printing unclosed lines is given in this paper. The further combination of phase-edge effects and phase-shifter size can also make it possible to form a wide range of patterns, ranging from line-space to isolated bright or dark areas with varied sizes, in a single exposure.
The use of the X-ray lithography to produce blazed diffractive optical elements (DOEs) is described. The proposed method allows one to make highly efficient blazed DOE with a deep phase profile (ten wavelengths and more) using a single X-ray mask with a binary transmission pattern. Unlike the well-known multilevel DOEs, blazed ones do not involve fabrication and aligning of a set of masks. DOEs with a profile depth of 10 micrometers and more and zone sizes of down to 1 micrometers can be obtained due to the short wavelength and high penetrability of X- rays. The first experimental samples of blazed DOEs with a 10 micrometers -height profile (lenses and gratings) were fabricated by X-ray lithography with synchrotron radiation using the X-ray masks, prepared in accordance with the pulse-width modulation algorithm. Diffraction efficiency for lenses was measured for white light. It is higher than 80 percent for the central part of the lenses (inside a 10 mm diameter) and about 60 percent for an area of 20 mm diameter.
Lithographic techniques for fabrication of hard x-ray Fresnel zone plates are discussed. Practical results achieved at the Center for X-ray Lithography of the University of Wisconsin- Madison are presented. Fabrication technology includes replication of an e-beam written master mask into a thick photoresist by synchrotron radiation x-ray lithography, and subsequent electroplating of a metal zone plate structure using photoresist pattern as a mold.
Deep X-ray lithography is a fabrication process for the production of a broad variety of microstructures with large structural heights. These can reach several hundred micrometers, with minimum lateral dimensions on the order of several microns. The main difference between ULSI and micromachining XRL is in the use of high-contrast masks (HCMs), with contrast in excess of 100. We fabricate these HCMs using a negative-tone resist to yield a coy of an original e-beam-made thin X-ray mask. Thus, we have fabricated HCMs with 6- micrometers -thick gold absorbers on SiN membranes using X-ray lithography replication. In our HCM fabrication process, it is possible to control the absorber sidewall by adjusting the exposure dose and development time. In this way, it is possible to generate absorbers sidewalls with slopes as large as 70 degrees. We have observed that when using HCM with sidewall slopes the exposed resist structures display sloping sidewalls as well. This opens the possibility of generating tapered structures and other complex shapes. This approach becomes even more interesting when combined with multilevel lithography, where different levels may be formed in the same resist layer by multiple exposures. We will present both experimental results and an image formation study that includes in detail the effect absorber topology, and the relation between mask sidewall slopes and resist sidewall slopes.
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