Natural physical phenomena occurring at length scales of a few nm in EUV lithography give rise to variation in photoresist images: edge, width, and top roughness, feature-to-feature CD or shape variability, edge placement errors, etc. The most damaging are stochastic printing failures caused by undesirable film thickness loss, admitting etch in line regions, or film thickness gain, preventing etch in space regions. In this work, we begin from analysis of well-calibrated rigorous physical stochastic EUV lithography models to study nanoscale exposure effects affecting stochastic failures. We apply acceleration to the stochastic model and perform computational inspection and classification of hot spots on a large layout area. The agreement between predicted probabilities of occurrence and observed defect frequencies are given for both line and space hot spots. We then perform computational inspection upon a virtual process and select hot spot locations and affect repairs. The actual mask is then fabricated, real wafers are exposed, processed, inspected and measured to compare the predicted reductions in defect probabilities with actual measured defect frequencies on wafer.
To maintain lithographic pitch scaling, extreme ultraviolet (EUV) processes have been adopted in high-volume manufacturing (HVM) for today’s advanced logic and memory devices. Among various defect sources, stochastic patterning defects are one of the most important yield detractors for EUV processes. In this work, we will limit our scope to patterning defects arising out of lithography. In the past, it has been shown that the patterning defect process window is often limited by stochastic hotspots. These hotspots have very low failure probabilities in a well-optimized process, and hence their detection necessitates large area sensitive defect inspection, such as with a broadband plasma (BBP) optical defect inspection system. It has also been shown that systematic issues in design can be exacerbated by stochastic variations. Hence, it is critical to discover these hotspots and study their variability with massive SEM metrology. Such analyses can uncover systematic trends, which can then be corrected and monitored. In this work, we discover hotspots using broadband plasma (BBP) optical inspection and study their variability using KLA’s aiSIGHT™ pattern-centric defect and metrology software solution for automatic defect classification and SEM metrology measurements. We also demonstrate the need for fast and rigorous 3D probabilistic stochastic defect detection on design as a continuation of this work.
Background: Natural physical phenomena occurring at length scales of a few nm produces variation in many aspects of the EUV photoresist relief image: edge roughness, width roughness, feature-tofeature variability, etc. 1,2,3,4. But the most damaging of these variations are stochastic or probabilistic printing failures 5, 6. Stochastic or probabilistic failures are highly random with respect to count and location and occur on wafers at spectra of unknown frequencies. Examples of these are space bridging, line breaking, missing and merging holes. Each has potential to damage or destroy the device, reducing yield 6, 10. Each has potential to damage or destroy the device, reducing yield 6, 10. The phenomena likely originates during exposure where quantized light and matter interact1 . EUV lithography is especially problematic since the uncertainty of energy absorbed by a volume of resist is much greater at 13.5 nm vs. 248 nm and 193 nm. Methods: In this paper, we use highly accelerated rigorous 3D probabilistic computational lithography and inspection to scan an entire EUV advanced node layout, predicting the location, type and probability of stochastic printing failures.
Our paper will use stochastic simulations to explore how EUV pattern roughness can cause device failure through rare events, so-called "black swans". We examine the impact of stochastic noise on the yield of simple wiring patterns with 36nm pitch, corresponding to 7nm node logic, using a local Critical Dimension (CD)-based fail criteria Contact hole failures are examined in a similar way. For our nominal EUV process, local CD uniformity variation and local Pattern Placement Error variation was observed, but no pattern failures were seen in the modest (few thousand) number of features simulated. We degraded the image quality by incorporating Moving Standard Deviation (MSD) blurring to degrade the Image Log-Slope (ILS), and were able to find conditions where pattern failures were observed. We determined the Line Width Roughness (LWR) value as a function of the ILS. By use of an artificial "step function" image degraded by various MSD blur, we were able to extend the LWR vs ILS curve into regimes that might be available for future EUV imagery. As we decreased the image quality, we observed LWR grow and also began to see pattern failures. For high image quality, we saw CD distributions that were symmetrical and close to Gaussian in shape. Lower image quality caused CD distributions that were asymmetric, with "fat tails" on the low CD side (under-exposed) which were associated with pattern failures. Similar non-Gaussian CD distributions were associated with image conditions that caused missing contact holes, i.e. CD=0.
Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning.
The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.
EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve
throughput has primarily been through a significant focus on source power which has been a continuing challenge
for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double
patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm
self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with
shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the
resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for
the patterned CD.
With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed
resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements
for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry
where the relaxation of both LER and CD together combined, give the resist formulation space a new target when
EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final
16nm half pitch target pattern to align with the industry needs.
If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow
proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed
process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added
costs associated with the double patterning process. This flow can then be shown to be an enabling approach for
many EUV applications.
EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.
In this paper we discuss the EUV OPC modeling challenges and potential solutions, as well as OPC integration
requirements to support the forthcoming application of EUV lithography. 10-nm-node OPC modeling is considered as
an example. Wafer and mask process data were collected for calibration and verification patterns, to understand the
mask making error/OPC model interactions. Several factors, including compact mask topography modeling impact, were
analyzed by means of rigorous simulations and model fitting. This was performed on a large-scale data set, to ensure
accurate characterization of the OPC modeling strategies, using a large number of patterns.
Several methods are evaluated to improve the accuracy of extreme ultraviolet (EUV) lithography OPC models by including additional physical effects which are not commonly used in deep ultraviolet (DUV) OPC. The primary additions to the model in this work are model based corrections for flare and two different corrections for mask shadowing effects, commonly referred to as HV bias. The quantitative, incremental, improvement from each of these additions is reported, and the resulting changes in tape-out flow and OPC runtime are discussed
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.
Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV)
lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new
non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must
be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work
will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology
nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and
mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and
compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV
because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.
The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with
possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV
lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will
postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm
node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm
immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing
with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion
lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography
technology as seen from an end-user perspective is summarized and the current values of the most important metrics for
each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into
production at the 14 nm technology node.
In this study, we have analyzed new data sets of pattern collapse obtained from 300 mm wafers which were coated with
a process-of-record (POR) EUV resist and exposed by an EUV Alpha-Demo tool (ADT) and a Vistec VB300 e-beam
exposure tool. In order to minimize any processing effects on pattern collapse, the same POR EUV track process was
applied to both exposures. A key metric of our analysis is the critical aspect ratio of collapse (CARC)1. We found that
CARC of POR EUV resist decreases monotonically with spacing, in the range of ~1.8-2.2 at ~32-54 nm space (60-80
nm pitch) for EUV, and ~1.5-2.1 at ~16-50 nm space (~46-80 nm pitch) for e-beam. We also estimated an apparent
Young's modulus of POR EUV resist by fitting a collapse model2 to the CARC data. The resulting modulus ~0.30 GPa
was much smaller than the modulus of typical polymer glasses (~1.0-5.0 GPa). Our findings suggest that due to a
significant decrease of resist mechanical properties and a sharp increase in capillary force, it will be challenging to
maintain aspect ratios above 2.0 for sub-30 nm resist spacing (sub-60 nm pitches). For patterning at these dimensions,
alternate processes and materials will become increasingly necessary, e.g. surfactant-based rinse solutions3 and other
approaches.
Spin-on underlayers are currently being employed by the lithographic industry to improve
the imaging performance of EUV resists. In this work, multiple examples have shown improved
line-edge roughness (LER) of an open-source resist using new open-source underlayers in
comparison to a primed silicon substrate. Additionally, several experiments demonstrate better
resist adhesion on underlayers that have lower coefficients of thermal expansion (CTE). Both
organic and inorganic underlayers provide better resist LER when their CTE is lower.
The development of resists that meet the requirements for resolution, line edge roughness and sensitivity remains one of
the challenges for extreme ultraviolet (EUV) lithography. Two important processes that contribute to the lithographic
performance of EUV resists involve the efficient decomposition of a photoacid generator (PAG) to yield a catalytic acid
and the subsequent deprotection of the polymer in the resist film. We investigate these processes by monitoring the
trends produced by specific masses outgassing from resists following EUV exposure and present our initial results. The
resists tested are based on ESCAP polymer and either bis(4-tert-butylphenyl)iodonium perfluoro-1-butanesulfonate or
bis(4-tert-butylphenyl)iodonium triflate. The components originating from the PAG were monitored at various EUV
exposure doses while the deprotection of the polymer was monitored by baking the resist in vacuum and detecting the
cleaved by-product from the polymer with an Extrel quadruple mass spectrometer.
This paper describes the lithographic properties of fifteen acid amplifiers (AAs) and the chemical modeling
approach used to predict their thermal stability in an ESCAP polymer resist system at 70 and 110 °C. Specifically, we
show how added AAs affect the sensitivity (Eo and Esize), resolution, line edge roughness (LER), exposure latitude, and
Z-parameter of ESCAP resists. We find that acid amplifiers that generate fluorinated sulfonic acids give the best
combination of sensitivity, LER, and exposure latitude. Additionally, we show that these compounds are not
photochemically active. Combining thermodynamic and kinetic modeling has allowed us to predict the relative enthalpies of activation for catalyzed and uncatalyzed decomposition pathways and compare the results to experimental
thermal stability tests.
The effect of higher film quantum yields (FQYs) on the resolution, line-edge roughness, and sensitivity (RLS)
tradeoff was evaluated for extreme ultraviolet (EUV, 13.5 nm) photoresists. We determined the FQY of increasingly
high levels of an iodonium photoacid generator (PAG) using two acid detection methods. First, base titration methods
were used to determine C-parameters for acid generation, and second, an acid-sensitive dye (Coumarin-6) was used to
determine the amount of acid generated and ultimately, to determine absorbance and FQYs for both acid detection
methods. The RLS performance of photoresists containing increasing levels of PAG up to ultrahigh loadings (5-40 wt%
PAG) was evaluated. RLS was characterized using two methods:
• KLUP resist performance
•Z-Parameter (Z = LER2*Esize*Resolution3)
Base titration methods are used to determine C-parameters for three industrial EUV photoresist platforms (EUV-
2D, MET-2D, XP5496) and twenty academic EUV photoresist platforms. X-ray reflectometry is used to measure the
density of these resists, and leads to the determination of absorbance and film quantum yields (FQY). Ultrahigh levels
of PAG show divergent mechanisms for production of photoacids beyond PAG concentrations of 0.35 moles/liter. The
FQY of sulfonium PAGs level off, whereas resists prepared with iodonium PAG show FQYs that increase beyond PAG
concentrations of 0.35 moles/liter, reaching record highs of 8-13 acids generated/EUV photons absorbed.
The 2007 International Technology Roadmap for Semiconductors (ITRS)1 specifies Extreme Ultraviolet (EUV)
lithography as one leading technology option for the 32nm half-pitch node, and significant world wide effort is being
focused towards this goal. Readiness of EUV photoresists is one of the risk areas. In 2007, the ITRS modified
performance targets for high-volume manufacturing EUV resists to better reflect fundamental resist materials challenges.
For 32nm half-pitch patterning at EUV, a photospeed range from 5-30 mJ/cm2 and low-frequency linewidth roughness
target of 1.7nm (3σ) have been specified. Towards this goal, the joint INVENT activity (AMD, CNSE, IBM, Micron,
and Qimonda) at Albany evaluated a broad range of EUV photoresists using the EUV MET at Lawrence Berkeley
National Laboratories (LBNL), and the EUV interferometer at the Paul Scherrer Institut (PSI), Switzerland. Program
goals targeted resist performance for 32nm and 22nm groundrule development activities, and included interim relaxation
of ITRS resist performance targets. This presentation will give an updated review of the results. Progress is evident in
all areas of EUV resist patterning, particularly contact/via and ultrathin resist film performance. We also describe a
simplified figure-of-merit approach useful for more quantitative assessment of the strengths and weaknesses of current
materials.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.