Presentation + Paper
10 April 2024 Advanced wafer engineering for minimizing overlay: tailoring and reducing wafer stress and distortion
Author Affiliations +
Abstract
We suggest advanced wafer engineering (i.e. Angle-ply Laminating Wafers(ALW)) which aim to tailoring and reducing wafer stress and distortion, in order to improve In-Cell Overlay(ICO) and On-Product Overlay(OPO). Especially, we focus ~nm devices adapting 3D-interconnection technology and scheme. In 3D-interconnection technology and scheme, Wafer to Wafer(W2W) bonding process are necessary harnessed. Unfortunately, it naturally induce large stress and distortion which are very sensitive to extrinsic and intrinsic property of wafer(i.e. initial warpage, thin film profile, wafer modulus). These wafer stress and distortion become a high risk in reducing overlay, as the cell size of device shrink. Thus, in development of ~nm devices, main key is to find effective and efficient method of wafer engineering reducing wafer stress and distortion. In order to handle this risk, we suggest and develop Angle-ply Laminating Wafers with heterogeneous crystal-structure, which is based on Classical Lamination Plate Theory(CLPT) in the area of advanced solid mechanics. By utilizing this design concept, anisotropic modulus of top and bottom wafer balance under W2W bonding process. As a result, it induce stress relaxation, distortion and reduce overlay. To verify it rigorously, we introduce the wafer stiffness tailoring method based on CLPT; and construct the simulation model predicting the W2W bonding distortion and photo overlay. We develop the W2W bonding simulation model based on framework of multiscale analysis and pre-verified by comparing with experiment results, which relate to the initial warpage effect on overlay and the thin film profile effect on bondability. Finally, we predict and analyze the effect of angle-ply laminating wafers with respect to a diverse combination of heterogeneous crystal-structure and stacking angle.
Conference Presentation
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Jong-Gu Lee, Hyeon-Jin Kim, JinMan Kim, HongJu Kim, Seok Heo, HaRam Ko, SungBin Jeon, YoungHa Kim, Jinhong Park, Hyunjae Kang, and Jeong-Gil Kim "Advanced wafer engineering for minimizing overlay: tailoring and reducing wafer stress and distortion", Proc. SPIE 12954, DTCO and Computational Patterning III, 129540D (10 April 2024); https://doi.org/10.1117/12.3010045
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KEYWORDS
Semiconducting wafers

Wafer bonding

Distortion

Overlay metrology

Deformation

Matrices

Crystals

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