We suggest advanced wafer engineering (i.e. Angle-ply Laminating Wafers(ALW)) which aim to tailoring and reducing wafer stress and distortion, in order to improve In-Cell Overlay(ICO) and On-Product Overlay(OPO). Especially, we focus ~nm devices adapting 3D-interconnection technology and scheme. In 3D-interconnection technology and scheme, Wafer to Wafer(W2W) bonding process are necessary harnessed. Unfortunately, it naturally induce large stress and distortion which are very sensitive to extrinsic and intrinsic property of wafer(i.e. initial warpage, thin film profile, wafer modulus). These wafer stress and distortion become a high risk in reducing overlay, as the cell size of device shrink. Thus, in development of ~nm devices, main key is to find effective and efficient method of wafer engineering reducing wafer stress and distortion. In order to handle this risk, we suggest and develop Angle-ply Laminating Wafers with heterogeneous crystal-structure, which is based on Classical Lamination Plate Theory(CLPT) in the area of advanced solid mechanics. By utilizing this design concept, anisotropic modulus of top and bottom wafer balance under W2W bonding process. As a result, it induce stress relaxation, distortion and reduce overlay. To verify it rigorously, we introduce the wafer stiffness tailoring method based on CLPT; and construct the simulation model predicting the W2W bonding distortion and photo overlay. We develop the W2W bonding simulation model based on framework of multiscale analysis and pre-verified by comparing with experiment results, which relate to the initial warpage effect on overlay and the thin film profile effect on bondability. Finally, we predict and analyze the effect of angle-ply laminating wafers with respect to a diverse combination of heterogeneous crystal-structure and stacking angle.
Scanners in High-Volume-Manufacturing conditions will experience a large range of reticles that vary in reticle transmission and reticle diffraction characteristics. Especially under full production loads reticles will heat up due to the exposure light-load and as such experience thermo-mechanical deformations. The resulting reticle pattern distortion can be partially translated in a deteriorated overall system overlay. Due to the geometry of the reticle and exposure fields, these reticle thermal effects are in general barrel-shape distortions that can be well corrected with the available set of lens manipulators. Nevertheless node-over-node the residual overlay errors associated with thermo-mechanical reticle deformation needs further reduction since it contributes to the total onproduct overlay performance. To reduce overlay caused by reticle temperature drift, NXT1980Di includes an active cooling mechanism suppressing the reticle temperature changes during exposure significantly. Even though the reticle temperature excursions are well suppressed, residual intra-wafer overlay drift effect can still be observed. Before exposure of a wafer, reticle deformation is measured during reticle align using in-line alignment / image sensors (TIS or PARIS). This is enabled by adding alignment markers around the circumference of the image field on the reticle. The measured reticle deformations are then fed to the system control network and dynamically corrected for by making use of the available manipulators in the scanner and the projection lens. Wafer-by-wafer reticle distortion measurements are performed to accurately capture the transient dynamics present in reticle heating during normal production lots. A new version of Reticle Heating Feed-forward Control (RHC2) is introduced that uses reticle-heating-induced deformation measurements over time and exposure sequence information to calibrate reticle-deformation-predictionmodels. These models are based on thermo-mechanical models that simulate reticle deformation under various exposure conditions and are applied in-line to the exposures to reduce intra-wafer overlay drift effects.
ASML’s 300mm scanner-systems are built on the TWINSCAN (XT/NXT) platform and yield high productivity levels for dry as well as immersion litho-scanners. NXT:1980Di immersion scanners yield productivity levels as high as 275wph while maintaining the overlay accuracy. The NXT:1980Di can be equipped with a new leveling mode that results in a significant reduction of the time that is spent on measuring the wafer focus height map. In the new leveling mode the focus height map is measured employing the full width of the level sensor and thereby minimizing the number of leveling scans. In this paper we describe the implementation of the LIL-method in the TWINSCAN platform design. Here, we report on the focus / leveling performance for both test as well as customer product wafers, and present a productivity outlook on the performance gain for a selected set of exposure use-cases.
As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.
Adjustment and control of the illumination pupil asymmetry is relevant for wafer alignment and overlay of lithography tools. Pupil asymmetries can cause a tilt in aerial image (Aerial Image Tilt, or AIT). This AIT, combined with a focus offset, leads to a horizontal image shift. Pupil asymmetries can be related to a shift of the entire illumination pupil (geometrical telecentricity) caused by illuminator misalign. Another type of pupil asymmetry is energetic imbalance (quantified by pupil Center of Gravity, COG). The scanner can show pupil variation across the exposure slit.
In general the COG at the edge of the slit is often worse than in the center part of the slit. Recently, ASML has released the NXT:1980Di that is equipped with an enhanced illuminator to improve pupil COG variation across the slit. In this paper we explore the performance of this scanner system and show that the AIT variation across the slit is also reduced significantly.
Overlay is one of the key factors which enables optical lithography extension to 1X node DRAM manufacturing. It is natural that accurate wafer alignment is a prerequisite for good device overlay. However, alignment failures or misalignments are commonly observed in a fab. There are many factors which could induce alignment problems. Low alignment signal contrast is one of the main issues. Alignment signal contrast can be degraded by opaque stack materials or by alignment mark degradation due to processes like CMP. This issue can be compounded by mark sub-segmentation from design rules in combination with double or quadruple spacer process. Alignment signal contrast can be improved by applying new material or process optimization, which sometimes lead to the addition of another process-step with higher costs. If we can amplify the signal components containing the position information and reduce other unwanted signal and background contributions then we can improve alignment performance without process change. In this paper we use ASML's new alignment sensor (as was introduced and released on the NXT:1980Di) and sample wafers with special stacks which can induce poor alignment signal to demonstrate alignment and overlay improvement.
In this paper we present the limitations of 3rd order distortion corrections based on standard overlay metrology and propose a new method to quantify and correct the cold-lens aberration fingerprint. As a result of continuous shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, most overlay enhancements were achieved by hardware improvements. However there also is a benefit in the computational approach, and so we looked for solutions for overlay improvements in process variation with computational applications.
Negative tone development (NTD) process with positive resist and organic solvent-based developer enhances image contrast and uses a light-field mask to make same feature in opposition to positive tone development (PTD). Due to extremely high transmission rate of a light-field mask, absorption of exposure energy on a mask becomes imperceptible. However, the exposure energy transmitted through the mask influences not only lens heating but also wafer heating. Overlay budget by wafer heating becomes a considerable amount in NTD process. In this paper, to clarify overlay change induced by wafer heating in NTD process, four different levels of exposure energy are applied and the overlay errors are deteriorated by increasing energy. Due to wafer heating, the remarkable correlation between Y-overlay errors and scanning direction are observed. Especially, Ty, RK8, and RK12 have mostly considerable correlation with scanning direction. In NTD process, to avoid this phenomenon, exposure energy has to be minimized. In case scanning direction dependency in overlay is not prevented by minimization of exposure energy, fingerprint correction in wafer field is able to reduce this overlay error.
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