Direct print extreme ultraviolet (EUV) has proven effective for pitch scaling and design rules flexibility. As feature size shrinks, stochastic noise poses challenges that demand innovative solutions. In this abstract, we present a novel approach known as pattern shaping , that not only addresses these challenges but also facilitates new opportunities for advanced patterning strategies. Integrating pattern shaping applications into the process flow reduces process complexity, eliminates the need for additional EUV patterning layers, paves the way for pushing lithographic print boundaries, and enhances the wafer yield. This accelerates the achievement of the technology readiness milestones.
R. Venkatesan, C. Guven, D. Bhawe, A. Greenwood, Z. Zhang, P. Gupta, P. Saksena, R. Rodriguez, N. Moumen, B. Bains, P. Sun, M. Aykol, C. Wallace, R. Bigwood, K. Fischer
This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of ~30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers. Careful co-optimization of the illumination source, photoresist and lithography stack is essential to resolve the tightest pitches. Optimum CDSEM metrology conditions and EUV specific requirements such as full field correction with thru slit, flare and black border compensation are critical to improve the quality of the optical proximity correction (OPC) flows. OPC algorithms were used to maximize the process window by using width sizing and pitch shifting to meet lithographic printability criteria while pushing mask manufacturability constraints to their healthy limits. The sizing of metal lines is modelled and fed to the RC extraction flows to close the fabdesign house feedback loop to improve accuracy of timing closure. A novel directional etch process enabled the direct print patterning of line tip-to-tips without requiring a second blocking mask. Multiple test masks were specifically designed to increase sensitivity of defect metrology and accelerate yield learning. Our results from multiple product vehicles demonstrate achievement of technology readiness milestones.
R. Venkatesan, C. Guven, D. Bhawe, A. Greenwood, Z. Zhang, P. Gupta, P. Saksena, R. Rodriguez, N. Moumen, B. Bains, M. Aykol, C. Wallace, R. Bigwood, K. Fischer
This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers. Careful co-optimization of the illumination source, photoresist and lithography stack is essential to resolve the tightest pitches. Optimum CDSEM metrology conditions and EUV specific requirements such as full field correction with thru slit, flare and black border compensation are critical to improve the quality of the optical proximity correction (OPC) flows. OPC algorithms were used to maximize the process window by using width sizing and pitch shifting to meet lithographic printability criteria while pushing mask manufacturability constraints to their healthy limits. The sizing of metal lines is modelled and fed to the RC extraction flows to close the fabdesign house feedback loop to improve accuracy of timing closure. Multiple test masks were specifically designed to increase sensitivity of defect metrology and accelerate yield learning. Our results from multiple product vehicles demonstrate achievement of technology readiness milestones.
Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moore's law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.
Conference Committee Involvement (1)
Photomask Technology
18 September 2007 | Monterey, California, United States
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