Dr. Earl E. Swartzlander Profile

Dr. Earl E. Swartzlander

Professor at Univ of Texas at Austin

SPIE Involvement:

Author

Publications (17)

Proceedings Article | 3 September 2009 Paper

Implementation of sort-based counters

Ryan Nett, Jay Fletcher, Earl Swartzlander

Proceedings Volume 7444, 74440R (2009) https://doi.org/10.1117/12.827306

KEYWORDS: Binary data, MATLAB, Systems modeling, Performance modeling, Computer programming, Algorithm development, Transistors, Fast packet switching, Data modeling, Roads

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Proceedings Article | 24 August 2009 Paper

Implementation of a speculative Ling adder

Malhar Mehta, Amith Kumar Nuggehalli Ramachandra, Earl Swartzlander

Proceedings Volume 7444, 74440K (2009) https://doi.org/10.1117/12.824730

KEYWORDS: Logic, Bismuth, Signal processing, Silicon, Clocks, Picosecond phenomena, Binary data, Error analysis, Multiplexers, Head

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Proceedings Article | 3 September 2008 Paper

Optimization of the final adder stage of fast multipliers

Sean Laughlin, Sabrina Smith, Paul Zucknick, Earl Swartzlander

Proceedings Volume 7074, 70740L (2008) https://doi.org/10.1117/12.794300

KEYWORDS: Logic, Picosecond phenomena, Very large scale integration, Visual process modeling, Multiplexers, Capacitance, Computer engineering, Structural design, Signal processing, Semiconductors

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Proceedings Article | 21 September 2007 Paper

An improved reciprocal approximation algorithm for a Newton Raphson divider

Gaurav Agrawal, Ankit Khandelwal, Earl Swartzlander

Proceedings Volume 6697, 66970M (2007) https://doi.org/10.1117/12.731650

KEYWORDS: Digital signal processing, Multiplexers, Electroluminescence, Computer engineering, Visualization, Signal processing, MATLAB, Data processing, Logic devices

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Proceedings Article | 25 August 2006 Paper

Optimization of spanning tree adders

Megha Ladha, Earl Swartzlander

Proceedings Volume 6313, 631301 (2006) https://doi.org/10.1117/12.681615

KEYWORDS: Picosecond phenomena, Transistors, Multiplexers, Signal generators, Logic, CMOS technology, Capacitance, Computer engineering, Signal processing, Resistance

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Proceedings Article | 16 September 2005 Paper

Impact of leakage on high-performance designs

Aniket Saha, Earl Swartzlander

Proceedings Volume 5910, 59100P (2005) https://doi.org/10.1117/12.617568

KEYWORDS: Logic, CMOS technology, Switches, Oxides, Transistors, Multimedia, Signal processing, Integrated circuit design, Molybdenum, Signal detection

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Proceedings Article | 26 October 2004 Open Access

The seven wonders of computer arithmetic

Earl Swartzlander

Proceedings Volume 5559, (2004) https://doi.org/10.1117/12.564467

KEYWORDS: Computer arithmetic, Binary data, Data corrections, Computing systems, Algorithm development, Signal processing, Logic, Matrices, Standards development, Computer engineering

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Proceedings Article | 26 October 2004 Paper

Automated synthesis of Dadda multipliers

Travis Lanier, Jacob Wilcox, Earl Swartzlander

Proceedings Volume 5559, (2004) https://doi.org/10.1117/12.559866

KEYWORDS: Computer aided design, Very large scale integration, Binary data, Logic, Computer engineering, Logic devices, Structural design, Metals, Resistance, Capacitance

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Proceedings Article | 24 December 2003 Paper

Efficient sign extension for multiple addition

Robert Grisamore, Earl Swartzlander

Proceedings Volume 5205, (2003) https://doi.org/10.1117/12.507644

KEYWORDS: Semiconductors, Computer engineering, Signal processing, Logic

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Proceedings Article | 24 December 2003 Paper

A comparison of Dadda and Wallace multiplier delays

Whitney Townsend, Earl Swartzlander, Jacob Abraham

Proceedings Volume 5205, (2003) https://doi.org/10.1117/12.507012

KEYWORDS: Computer engineering, Logic, Signal processing, Computer architecture, Binary data

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Proceedings Article | 6 December 2002 Paper

Constant-delay MSB-first bit-serial adder

Chang Yong Kang, Earl Swartzlander

Proceedings Volume 4791, (2002) https://doi.org/10.1117/12.451778

KEYWORDS: Clocks, Binary data, Computer engineering, Computer architecture, Signal processing, Logic, Computing systems, Neck

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Proceedings Article | 6 December 2002 Paper

Design of a hybrid prefix adder for nonuniform input arrival times

Youngmoon Choi, Earl Swartzlander

Proceedings Volume 4791, (2002) https://doi.org/10.1117/12.452040

KEYWORDS: Multiplexers, Bismuth, Computer engineering, Signal processing, Evolutionary algorithms, Binary data

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Proceedings Article | 20 November 2001 Paper

Optimal design method for fast carry-skip adders

Songjun Lee, Earl Swartzlander

Proceedings Volume 4474, (2001) https://doi.org/10.1117/12.448646

KEYWORDS: Algorithm development, Logic devices, Astatine, Logic, Computer engineering, Signal processing, Signal generators

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Proceedings Article | 13 November 2000 Paper

Fast multiply-accumulate architecture

Robert Grisamore, Earl Swartzlander

Proceedings Volume 4116, (2000) https://doi.org/10.1117/12.406506

KEYWORDS: Digital signal processing, Signal processing, Computer architecture, CMOS technology, Finite impulse response filters, Standards development, Clocks, Computer engineering, Broadband telecommunications, Telecommunications

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Proceedings Article | 13 November 2000 Paper

Hybrid pipelined and multiplexed FIR filter architecture

Waqas Akram, Earl Swartzlander

Proceedings Volume 4116, (2000) https://doi.org/10.1117/12.406509

KEYWORDS: Multiplexing, Finite impulse response filters, Optical filters, Filtering (signal processing), Logic, Computer architecture, Time division multiplexing, Multiplexers, Clocks, Digital signal processing

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Proceedings Article | 2 November 1999 Paper

Fault-tolerant arithmetic via time-shared TMR

Earl Swartzlander

Proceedings Volume 3807, (1999) https://doi.org/10.1117/12.367623

KEYWORDS: Tolerancing, Multiplexers, Computer engineering, Internet, Signal processing, Demultiplexers, Logic, Plutonium

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Proceedings Article | 2 October 1998 Paper

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