Optimization of spanning tree adders

Megha Ladha; Earl E. Swartzlander Jr.

doi:10.1117/12.681615

25 August 2006 Optimization of spanning tree adders

Proceedings Volume 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI; 631301 (2006) https://doi.org/10.1117/12.681615
Event: SPIE Optics + Photonics, 2006, San Diego, California, United States

Abstract

This paper compares several designs of spanning tree adders for 16 and 32 bit widths. The carry select part of the spanning tree is done using ripple carry and carry skip adders (4, 8 and 16 bits) and compared in terms of delay, complexity and power consumption. The spanning tree design is also compared with that of a conventional carry lookahead adder. All the designs are done using only 2 input NAND and NOR gates and inverters in 0.18 μm CMOS technology. The delay and power consumption is determined by use of simulations performed with Synopsys and Cadence design tools. The spanning tree adder realized with carry skip adders is about 40% faster than the carry lookahead adder with an approximate increase of 17% in complexity and 22% in power.

Citation Download Citation

Megha Ladha and Earl E. Swartzlander Jr. "Optimization of spanning tree adders", Proc. SPIE 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 631301 (25 August 2006); https://doi.org/10.1117/12.681615

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