Efficient sign extension for multiple addition

Robert T. Grisamore; Earl E. Swartzlander Jr.

doi:10.1117/12.507644

24 December 2003 Efficient sign extension for multiple addition

Robert T. Grisamore, Earl E. Swartzlander Jr.

Proceedings Volume 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII; (2003) https://doi.org/10.1117/12.507644
Event: Optical Science and Technology, SPIE's 48th Annual Meeting, 2003, San Diego, California, United States

Abstract

A technique for reducing the sign extension overhead in adder trees is presented. A generalized version of the technique is shown to reduce the number of redundant sign extension computations required for reducing parallel adder trees from N terms to two terms. Additionally, the technique eliminates the fan-out latency that traditional sign extension places on late arriving sign bits. Twos complement number growth is also managed in carry-save form without the need for carry propagation. The application of the technique to 2N term adder trees is demonstrated. The implementation requires no computational overhead and needs minimal hardware. This design not only reduces hardware complexity, but also reduces computation delay. Finally, a simple circuit transformation to the traditional 4-2 compressor allows simple construction of circuits utilizing the technique.

Citation Download Citation

Robert T. Grisamore and Earl E. Swartzlander Jr. "Efficient sign extension for multiple addition", Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); https://doi.org/10.1117/12.507644

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