Today, we are at the dawn of the 5th disruptive innovation wave. This emerging fifth wave, the deeptech wave, builds on the convergence of technologies such as AI, material science, biology, semiconductors … to disrupt virtually every aspect of the physical world we live in. Semiconductors will be the core of many deeptech innovations thanks to their massive integration power, accessible mass production and low cost. To enable these deeptech innovations, Moore’s law will have to continue to address insatiable demands for more computation and more storage. We will realize Moore’s law by a multitude of approaches: continue traditional scaling, new devices, new switches, leverage the use of the third dimension, and paradigm shifts on how to build future systems. The challenges to bring these innovations to the market are huge. Therefore, we will have to approach this evolution through a major ecosystem, bringing together the right companies, the right R&D resources, perform this in leading-edge infrastructure, with the right funding and government support.

The semiconductor industry has been extremely successful in integrating discrete components into billion-transistor chips. Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades. Applications such as AI, machine learning, 5G, and even quantum computing, will not fulfill their promises without the continual advancements of semiconductor technology that is anticipated. Advancement of lithography has always been viewed as one of the most important, if not the most important, technologies that enables generations after generations of semiconductor technologies. With EUV and the upcoming high NA tools, it appears that there will be enough patterning resolution to pattern anything we want, unless we need to carve individual atoms. What is the future of lithography? What problems can lithography solve for the semiconductor industry? I will present industry and technology trends as a seed corn for discussion.

Quantum computing is the grand challenge of the 21st century and is poised to revolutionizes our daily lives on a nearly unfathomable level. To truly understand the impact, we must first build a universal, fully error corrected machine capable of exploring the application space envisioned by both academic and industry. Numerous pathways have been identified and demonstrated to fabricate single, unique qubits using a myriad of platforms (superconducting, ions, nanoparticles, photons, etc…). However, it is now widely accepted that a truly useful quantum computer will require millions of interconnected, identical qubits to perform fully error corrected, general purpose calculations. To that end, photon-based qubits offer a path to such a general-purpose machine by leveraging the mature silicon photonics high-volume manufacturing ecosystem. Creating quantum devices from silicon photonics components requires patterning innovation to bring leading-edge nanolithography to near macroscopic scale, a unique challenge for an industry where the future relies on progressive device shrink.

Since first demonstrating viable Nanosheet technology in the last decade, IBM Research has continued to innovate to bring this technology to the maturity, density, and performance required to be the clear successor to FinFET CMOS technology. This innovation was recently discussed in the latest “2nm node” announcement from IBM. A Nanosheet transistor at these dimensions, with this level of complexity, does not even function (let alone hit yield and performance targets) without significant advancements in metrology and control techniques. This talk will discuss the metrology enablers that foster process breakthroughs, as well as discuss what needs to come next in order to realize the next decade of stacked nanosheet transistor innovation.

SEM-based imaging techniques play a strong role in logic semiconductor manufacturing metrology. SEM-based detection techniques have, historically, played a lesser role in inspection, where the objective is defect detection and not imaging. Electron beam inspection (EBI) has seen adoption to monitor systematic defects, with modest area coverage requirements, but it has not been adopted to drive final yield ramp nor for high volume line control due to area coverage challenges at reasonable throughputs. Full logic, yield ramp requires detecting and reducing defect levels from 10^10 per square centimeter levels down to 10^-2. Line control requires measuring enough area to detect excursions from a 10^-2 defects per square centimeter baseline in a factory starting tens of thousands of wafers per month. This first section of this paper reviews the area scaling challenges in detail, stressing the innovation and creativity required to scale SEM as the brute force methods employed by traditional optical inspection systems are not available for EBI. The second section of the paper reviews the design parameter palette available to the EBI developers. The design decisions involving these parameters are mapped to logic yield applications, and the opportunities for future throughput scaling, and more extensive yield ramp and control support, are discussed.

We implement an elegant hardware upgrade in our EUV imaging reflectometer to significantly reduce noise from beam power fluctuations. Our instrument non-destructively characterizes the composition and morphology of samples both transversely and depth-resolved, by implementing an EUV coherent diffractive imaging (CDI) microscope in a variable-angle reflection geometry. This upgrade significantly improves signal-to-noise ratio (SNR) by using an EUV beam splitter to simultaneously monitor the beam intensity before and after reflection from the sample. Fluctuations in power may then be normalized out, resulting in greatly improved SNR — an enhancement of ~6x in our first, non-optimized implementation.

Sidewall roughness of a photoresist pattern is important information to consider such as a relation between LERs (or LWRs) of the resist and etched pattern. It is well known that sidewall of a dry-etched Si pattern shows vertical striations (anisotropic roughness) [Kizu et al., JM3 19, 014003 (2020)]. On the other hand, in the case of photoresist, although there are several studies about photoresist sidewall roughness, neither high-resolution sidewall measurement nor roughness evaluation techniques has been established. In this study, we measured photoresist sidewall with high-resolution using a metrological tilting-AFM, which is able to measure vertical sidewall of a line pattern owing to tilted AFM-probe. The result showed the photoresist sidewall roughness has height dependency in contrast to that of a Si line pattern. Further result and discussion will be presented in the conference.

In the semiconductor manufacturing process, performing metrology over 2D complex features is mandatory for advanced technology nodes. Top-down critical dimension scanning electron microscopes (CD-SEMs) are widely used for many applications and are key enablers for metrology and process control. Nevertheless, one of the limitations one may observe when using CD-SEMs is the contrast variation (or lack of contrast) in areas where the pattern edges are parallel to the CD-SEM acquisition scan direction, which may lead to accuracy and precision loss. Model-based contour extraction solutions are often able to address this reduction in contrast while maintaining the accuracy and precision required by the different usages. However, for particularly low contrast/low SNR images, this may lead to a reduction in accuracy of the metrology process. This work explores the concept of hybrid contours generation, combining contours – coming from different scan directions – with pattern fidelity metrics, in order to overcome the issues related to edge detection accuracy and precision, especially in 2D shapes. It brings the advantage of combining relevant information from each image, weighted based on their reliability, which is estimated by a combination of the scan direction and the fidelity of the edge profile observed on the patterns. This method of combining contours improve 2D measurements and is also the most reliable way of building contours for OPC modeling, among other uses.

Achieving and maintaining top SEM performance, ensuring excellent tool matching involves optimization of more than a couple of the attributes of the SEM. Objective instrument quality/performance assessment requires suitable measurement methods and associated reference samples. The electron probe size, shape, direction (incidence angle), are essential inputs for simulation that can be used to fully optimize measurements for speed and reliable data, and for model-based SEM measurements that provides the best, most accurate dimensional measurement results. The presentation addresses these problems by presenting suitable measurement solutions and sample designs.

We present a novel method that can automatically correct astigmatism and focus error with great accuracy in the scanning electron microscopy (SEM). Here, an iterative deconvolution method and the feature-based compensation algorithm were applied to the beam control sequence, enabling us to obtain the clear SEM image without any distortion. A proof of concept was fully verified by both mathematical analysis and experimental results. By utilizing the proposed method, accurate beam profile optimization is possible without malfunction even when imaging a sample with anisotropic pattern.

This work proposes a methodology to characterize the extent of photoresists’ CD shrink from various SEM landing energy and imaging conditions, using both AFM metrology and post-etch pattern transfer as methods to evaluate the true physical CD. The resist shrink for both 1D and 2D features with varying resist volumes can be quantified through the various metrology techniques and post-etch dimensional data. Once characterized, material response during SEM exposure can be accounted for in any CDSEM data comparison or OPC model.

This Conference Presentation, “A holistic study of edge placement error on fin cut layer in self-aligned double patterning process,” was recorded at SPIE Photonics West held in San Francisco, California, United States.

To detect anomalies/defects for random/arbitrary IC patterns, we decompose SEM images into small sub-images and apply an identical autoencoder to each of them. The astronomical varieties in random IC patterns are reduced into limited varieties in elementary patterns, which are coded onto limited dimension latent vectors in autoencoder. A wide variety of anomalies/defects are detected with neither design data nor prior knowledge about defects at a high SNR with practical throughput. It also captures a small sign of change in process conditions and pattern fidelity and will be effective for inspection in EUV patterning using high-speed SEMs.

The transition from finFETs to nanosheet transistors is on. The industry is therefore looking into the options for a subsequent device, among which forksheet transistors appear as a serious contender [1]. Common to the processing of these Gate-All-Around architectures, the cavity etch, wherein SiGe is etched laterally from a SiGe/Si multilayer, remains a step of paramount importance [2]. Its development therefore requires new techniques for geometrical and material characterization. In this paper, we elaborate on the use of top-down spectroscopic techniques [3] to measure critical parameters such as cavity depth, stress and SiGe residues in nanosheet and forksheet transistors.

Improved resolution of the High-NA EUV technology comes with thinner photoresist and smaller aspect-ratio requirements. Trade-offs include more stringent process control needs for resist loss and line roughness. Traditional metrologies like OCD or CD-SEM lose sensitivity due to diminishing interaction volume. A metrology technique that thrives in this regime is Scanning Probe Microscopy: thinner resist allows for higher scanning speed, and smaller aspect ratio for higher measurement accuracy. Here we propose a High-Throughput SPM technique as key enabler for High-NA EUV process control. Detailed, high-density full wafer measurements of resist loss, CD and roughness are enabled by a high-throughput, 4-head SPM toolset, and compared for different resist thicknesses down to 10nm. Sampling schemes consistent with scanner throughput are considered.

Magnetoresistive random-access memory (MRAM) technology and recent developments in fabrication processes have shown it to be compatible with Si-based complementary metal oxide semiconductor (CMOS) technologies. The perpendicular spin transfer torque MRAM (STT-MRAM) configuration opened up opportunities for an ultra-dense MRAM evolution and was most widely adapted for its scalability. Insertion of STT-MRAM in the back end of line (BEOL) wiring levels has many advantages, including density, latency, and endurance with the promise of being comparable to performance of dynamic random access memory technology (DRAM). There are several important parameters at multiple process steps which require precise metrology for STT-MRAM integration. Inline metrology of the magnetic tunnel junction (MTJ) pillar is vital to calibrate the magnetic read/write performance parameters. This work discusses various challenges to monitor critical process steps for integrating STT-MRAM in advanced CMOS technologies and key metrology solutions are presented. To precisely predict MRAM junction resistance early in the process flow, a machine learning model was developed using scatterometry spectra collected after MTJ pillar formation and corresponding resistance data from the end of line electrical test. This machine learning model utilizes metrology data from the pillar formation process and can predict accurate device resistance values. Additionally, carefully monitoring the required planarization process of an interlayer dielectric deposited after the MTJ pillar formation is critical to avoid subsequent defects. Several modelling techniques are discussed and a new spectral interferometry-based technique, vertical travelling scatterometry (VTS), is demonstrated as a solution for measurements on fully integrated device areas.

In this research work, we have demonstrated the application of Mask-RCNN (Regional Convolutional Neural Network), a deep-learning algorithm for computer vision and specifically object detection, to semiconductor defect inspection domain. Defect detection and classification during semiconductor manufacturing has grown to be a challenging task as we continuously shrink circuit pattern dimensions (e.g., for pitches less than 32 nm). Current state-of-the-art optical and e-beam inspection tools have certain limitations as these tools are often driven by some rule-based techniques for defect classification and detection. These tool/software limitations often lead to misclassification which necessitates manual classification. In this work, we have revisited and extended our previous deep learning-based defect classification and detection method [1] for improved defect instance segmentation in SEM images with precise extent of defect as well as generating a mask for each defect category/instance. This also enables to extract and calibrate each segmented mask and quantify the pixels that make up each mask, which in turn enables us to count each categorical defect instances as well as to calculate the surface area in terms of pixels. This paper aims at detecting and segmenting different types of defect patterns such as bridges, breaks and line collapse as well as to differentiate accurately between multi-categorical defect bridge scenarios (as thin/single/multi-line/horizontal/non-horizontal) for aggressive pitches as well as thin resists (High NA applications). Our proposed approach demonstrates its effectiveness both quantitatively and qualitatively.

3D topography imaging systems such as Atomic Force Microscopy (AFM) are used for surface characterization and metrology in numerous contexts especially when nanometer resolution is required (e.g. semiconductor industry & research). During the acquisition of an AFM image often a drift is present in vertical direction that is superimposed on top of the topography signal. This represents an artefact that cannot be removed with a single one-size-fits-all algorithm and typically requires manual input and expert assessment whether the correction is done appropriately. Hence, the final result is operator dependent. In this work we propose a method to correct various artifacts that arise from vertical (Z) drift that can be regarded a superimposed envelope (ENV) on top of the true topography of the sample. We remove this envelope with the help of processing the raw image data with the help of Deep Neural Networks. Moreover, we employ a normalization scheme for pixel intensities for the preservation of absolute vertical height values for corrected images thus allowing for quantitative measurements of topography for metrology needs. Our approach allows for automatic and operator independent data correction, leading to more robust data analysis and interpretation, enabling faster speed of learning

To further enhance performance of in-line XPS metrology we will demonstrate the benefit of an unsupervised machine learning approach to increase precision of critical metal gate film thickness measurements and quantification of doping concentration within source-drain junctions. Unsupervised ML efficiently separates process information from inherent noise in the XPS spectra to enable a noise-filtering that improves result precision. The observed precision improvements were utilized to increase wafer through-put by reducing the acquisition time while preserving precision, accuracy, and sensitivity when supporting high volume manufacturing.

The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted and construction metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. With the consideration of the data consistency and to create a unified method to serve as an industry standard we evaluated 3 approaches: equation based, polygon based, measurement based – to calculate / combine / measure the device EPE. Results will be discussed in the presentation

The performance of electrical circuits depends highly on the overlay of the actual device. However, overlay metrology is typically performed on dedicated non-device structures as proxy for device. In this paper, we show that an overlay metrology system based on high voltage scanning electron microscope (HV-SEM) can be used to measure the overlay errors of devices of any shape using a die-to-database (D:DB) algorithm. The D:DB algorithm uses the design-intent of multiple layers, in the form of database clips, to extract overlay errors for patterns of any shape. The D:DB algorithm can account for edge-over-edge effects as well as multiple visible layers at once. This enables accurate overlay measurements, even for complex devices, while simultaneously reporting overlay for multiple layer pairings. We show that this method of device measurement can be used to compare how the overlay error reported by different target designs matches the overlay error of the device structures itself.

The insertion of sub-resolution assist features as part of the optical proximity correction flow is one of the main elements of advanced resolution enhancement techniques. It needs to be ensured that there is no unintentional printing of such a sub-resolution assist feature in the photoresist since it would detract the product yield. To be able to prevent unintentional printings, a robust printing prediction simulation model is required. The calibration of such a model can be challenging since common CD-SEM measurements cannot be used to quantify such small sized printings at a poor contrast. The assessment of SEM images through human judgement is inefficient and somewhat subjective to errors. In this work, we propose an automated method to quantify SRAF printing through layout assisted SEM image analysis. The motivation is to get a fast and objective model calibration thanks to the automation and the absence of human judgement.

The idea to better use the thousands of CD-SEM (critical dimension scanning electron microscope) images that are acquired daily in a fab has been a driver since few years now [1,2]. In previous publications, we advocated for a remote image computing toolbox integration into the wafer fab. Such system would be based on an image computing environment (outside the metrology tools and outside the wafer fab) connected to databases and data-analytic tools so that CD-SEM image information could be enriched by the usage of more complex image treatment tool such as a CNN (convolutional neural network) for qualitative information or image analysis and contour extraction for quantitative and qualitative information. Contour based metrology offers a wide range of “new” measurements capability solutions [2,3,4] which are of interest for the process support (R&D or Production) but also for metrology equipment owners. Expressing the added value of a remote metrology toolbox on top of the existing one from metrology tool themselves is not necessarily an easy task. It is often related to use cases that will really show good return on investment. Many examples of what can be achieved with contour metrology have been published, even with thousands of images computed, but it remains far from being seen as production worthy if not experienced in real time. Based on encouraging preliminary results on valuable data extracted using remote metrology software, a proof-of-concept integration on manufacturing data was put in place in order to gather direct feedback to the fab. This paper will describe how an image computing software has been integrated to the data infrastructure of our wafer fab so that every CD-SEM image is being processed outside the CD-SEM equipment to monitor the image quality on one side (so the CD-SEM tool stability) and perform measurements on the other side. Results extracted from inline contour-based image computing over several months’ worth of data will be presented showing some of the benefits of integrating edge computing solutions in wafer fab production flow.

Defect inspection in semiconductor processes has become a challenging task due to continuous shrink of device patterns (pitches less than 32 nm) as we move from node to node. Current state-of-the-art defect detection tools (optical/e-beam) have certain limitations as these tools are driven by some rule-based techniques for defect classification and detection. These limitations often lead to misclassification of defects, which leads to increased engineering time to correctly classify different defect patterns. In this paper, we propose a novel ensemble deep learning-based model to accurately classify, detect and localize different defect categories for aggressive pitches and thin resists (High NA applications).In particular, we train RetinaNet models using different ResNet, VGGNet architectures as backbone and present the comparison between the accuracies of these models and their performance analysis on SEM images with different types of defect patterns such as bridge, break and line collapses. Finally, we propose a preference-based ensemble strategy to combine the output predictions from different models in order to achieve better performance on classification and detection of defects. As CDSEM images inherently contain a significant level of noise, detailed feature information is often shadowed by noise. For certain resist profiles, the challenge is also to differentiate between a microbridge, footing, break, and zones of probable breaks. Therefore, we have applied an unsupervised machine learning model to denoise the SEM images to remove the False-Positive defects and optimize the effect of stochastic noise on structured pixels for better metrology and enhanced defect inspection. We repeated the defect inspection step with the same trained model and performed a comparative analysis for “robustness” and “accuracy” metric with conventional approach for both noisy/denoised image pair. The proposed ensemble method demonstrates improvement of the average precision metric (mAP) of the most difficult defect classes. In this work we have developed a novel robust supervised deep learning training scheme to accurately classify as well as localize different defect types in SEM images with high degree of accuracy. Our proposed approach demonstrates its effectiveness both quantitatively and qualitatively.