Mr. Thibaut Bourguignon Profile

Thibaut Bourguignon

SPIE Involvement:

Author

Publications (5)

Proceedings Article | 5 October 2023 Paper

Understanding the impact of rinse on SEM image distortion and hole patterning variability

Elvire Soltani, Bertrand Le-Gratiet, Sébastien Bérard-Bergery, Jonathan Pradelles, Thibaut Bourguignon, Aurélie Le Pennec, Nathalie Charras, Raluca Tiron

Proceedings Volume 12802, 1280209 (2023) https://doi.org/10.1117/12.2675586

KEYWORDS: Semiconducting wafers, Distortion, Scanning electron microscopy, Metrology, Image processing, Contour extraction, Optical lithography, Lithography, Data modeling, Critical dimension metrology

Read Abstract +

Background: Stochastic effects are manifested by local variabilities in critical dimension (CD), shape, size and placement of patterns. On previous works, a commercial software has been used to extract contours from CDSEM images, from which various metrics are computed to quantify these variabilities. Last year, an image processing system has been implemented to monitor these indicators in a high-volume manufacturing (HVM) environment. This system automatically extracts these contour-based metrics from the in-line images. Aim: The study has been divided into two parts. The first objective was to show the ability to detect a mismatch between two lithography clusters, not revealed by traditional CD in-line trends. Since investigations identified that this mismatch was caused by differences in the rinse recipes, the second objective was to gain a deeper understanding of the impact of rinse on both metrology and patterning. Approach: In addition to the traditional CD measurements, the following metrics are also monitored: Local CD Uniformity (LCDU), Pattern CD Uniformity (PCDU) and Centroid Shift Uniformity (CSU). Results: Baselines for the 28 nm contact process have been established, providing new indicators to compare and monitor processes and tools in the fab. PCDU computed on post-lithography images proved to be an effective detector of clusters mismatching, not identified by the CD criterion. Upon investigation, engineers discovered differences in the rinse recipes between the two lithography tools. To analyze the influence of rinse, an R&D experiment was conducted, repeating this very same step 2, 4 and 6 times in a row. As rinse steps number increased, two observations have been made: SEM images are more distorted, and the shape variability indicator (PCDU) increases. The most likely explanation is that increased friction with the deionized water during the rinse results in more stored electrical charges at the wafer surface, which affects the resist (increased “roughness”) and disturbs the SEM image acquisition. Conclusions: By implementing a remote metrology system to perform extensive analysis of in-line CD-SEM images with a contour extraction software, a cluster mismatching (not from the CD point of view) was identified in a HVM environment. This enhanced in-line monitoring enabled us to find the parameter to be adjusted to match them, thereby avoiding any adverse effects. Experiments confirmed that rinse negatively affects both SEM image fidelity (increased distortion) and process uniformity (decreased shape uniformity).

Proceedings Article | 27 April 2023 Presentation + Paper

High spatial frequency on-device overlay characterization using CD-SEM contours

Thibaut Bourguignon, Bertrand Le Gratiet, Jonathan Pradelles, Sébastien Bérard-Bergery, Charles Valade, Nivea Schuch, Nicolas Possémé

Proceedings Volume 12496, 124960J (2023) https://doi.org/10.1117/12.2657914

KEYWORDS: Scanning electron microscopy, Overlay metrology, Data modeling, Optical testing, Metrology, Contour extraction, Lithography, Design and modelling

Read Abstract +

The on-device and target-less overlay (OVL) measurement adds various challenges to the conventional target-based one.¹ Most of the common solutions are based on the use of high voltage SEM to have a high resolution and see-through capabilities to see both layers entirely. To ensure repeatability and robustness the measurement is also generally realized on dedicated targets.^2–4 Another approach is explored in this work : it consists of a direct measurement on the device itself, without any dedicated target and using a CD-SEM that do not have see-through capabilities. To avoid any damage on the final device and to ensure a partial vision of the bottom layer, the measurement is realized post etch. What can a true on-device, target-less, SEM overlay metrology reveal of the process? To answer this question, a custom design-based on-device CD-SEM overlay metrology was developed.⁵ It allows measuring the overlay on any bilayer 2D structure, even partially hidden, provided that sufficient edges are visible. Thanks to this post-processing capacity to measure on partially hidden patterns, the CD-SEMs from the current tool park can be used and non-transparent layers can be investigated. After demonstrating the capability of the previously mentioned solution on synthetic SEM images,⁶ by taking advantage of the versatility of the method and of an improved bilayer contour extraction algorithm, one product wafer was measured densely at different steps of the process on several patterns. These extensive measurements aim to reveal overlay signatures at different spatial frequencies: intra-field, intra-chip and even inside a random logic array. This paper details and interprets the observed overlay measurement with models while investigating the matching between the different measurement patterns and the mismatches with the optical overlay. To conclude, the contour-based metrology offers the capability to extract highly valuable information from CD-SEM images and represents a great opportunity for on-device overlay measurement. By measuring directly the products’ patterns, the developed metrology shows a mismatch between optical and SEM measurements up to a couple of nanometers. A hybrid model, mixing SEM and optical measurements reduced by 15% the on-product residuals. Additionally, the local overlay variability could be evaluated and low amplitude chip signatures have been observed. This new information will help process engineers to improve the process characterization, leading to a better process control that results in an improved reliability.

Proceedings Article | 1 November 2022 Paper

Contour based on-device overlay metrology assessment using synthetic SEM images

Thibaut Bourguignon, Bertrand Le Gratiet, Jonathan Pradelles, Sébastien Bérard-Bergery, Guido Rademaker, Nicolas Possémé

Proceedings Volume 12472, 124720C (2022) https://doi.org/10.1117/12.2640140

KEYWORDS: Overlay metrology, Scanning electron microscopy, Monte Carlo methods, Metrology, Image processing, Image quality, Semiconducting wafers, Reliability

Read Abstract +

The shift of semiconductor industry applications into demanding markets as spatial and automotive led to high quality requirements to guaranty good performances and reliability in harsh environments. As reliability is directly related to a well-controlled process, characterizing the local overlay and its variations inside the chip itself becomes a real asset. While most available in-chip overlay metrologies require dedicated target or dedicated tools, we developed a new method that aims to augment the current SEM tool park into measuring the local overlay directly on the product. In a previous proceeding, this on-device and target-free overlay measurement based on CD-SEM contours has been assessed on SRAM patterns and showed promising results. The work presented here pushes forward this assessment using SEM synthetic images generated from the open-source Nebula simulator of electron-matter interaction. From a layout, a 3D geometry of the measured pattern can be generated, with materials and interfaces carefully defined. Then, a GPU-accelerated Monte-Carlo model simulates in tens of seconds the SEM image. This fast generation of images enables the use of synthetic SEM images in a digital twin system: they can be used to characterize and to challenge the overlay metrology, before applying it to real products. Indeed, a known overlay can be programmed in these images. This way the performances of the measurement algorithm can be assessed with a ground truth reference. Firstly, imaging parameters such as pixel size and noise have been varied in a wide range. This demonstrated a good accuracy and precision inside a defined measurement window with a coefficient of correlation above 0.996 and an offset lower than 0.2nm. In a second part, the influence of the pattern measured has been investigated and experimental results on SRAM could be reproduced using synthetic images. The origin of the loss of sensitivity has been identified and improvements in the contour extractions and used template led to a correlation with a slope of 1.03, an offset of 0.1nm and a Root Mean Square Deviation of 1.36 nm. Finally, the developed digital twin already showed behaviors in the measurement that were hidden in the on-wafer experiments, that helped assessing the method and which will be used in the future to define guidelines for template-based SEM-OVL measurements.

Proceedings Article | 14 June 2022 Poster + Paper

A proof of concept of remote contour-based SEM metrology integration in HVM environment

Bertrand Le Gratiet, Régis Bouyssou, Julien Ducoté, Florent Dettoni, Thibaut Bourguignon, Vincent Morin, Romain Bange, Nivea Schuch, Julien Nicoulaud, Guillaume Renault, Frederic Robert, Thiago Figueiro

Proceedings Volume PC12053, PC120530S (2022) https://doi.org/10.1117/12.2615199

KEYWORDS: Metrology, Semiconducting wafers, Data integration, Visualization, Time metrology, Scanning electron microscopy, Manufacturing, Image quality, Image processing software, Image processing

Read Abstract +

The idea to better use the thousands of CD-SEM (critical dimension scanning electron microscope) images that are acquired daily in a fab has been a driver since few years now [1,2]. In previous publications, we advocated for a remote image computing toolbox integration into the wafer fab. Such system would be based on an image computing environment (outside the metrology tools and outside the wafer fab) connected to databases and data-analytic tools so that CD-SEM image information could be enriched by the usage of more complex image treatment tool such as a CNN (convolutional neural network) for qualitative information or image analysis and contour extraction for quantitative and qualitative information. Contour based metrology offers a wide range of “new” measurements capability solutions [2,3,4] which are of interest for the process support (R&D or Production) but also for metrology equipment owners. Expressing the added value of a remote metrology toolbox on top of the existing one from metrology tool themselves is not necessarily an easy task. It is often related to use cases that will really show good return on investment. Many examples of what can be achieved with contour metrology have been published, even with thousands of images computed, but it remains far from being seen as production worthy if not experienced in real time. Based on encouraging preliminary results on valuable data extracted using remote metrology software, a proof-of-concept integration on manufacturing data was put in place in order to gather direct feedback to the fab. This paper will describe how an image computing software has been integrated to the data infrastructure of our wafer fab so that every CD-SEM image is being processed outside the CD-SEM equipment to monitor the image quality on one side (so the CD-SEM tool stability) and perform measurements on the other side. Results extracted from inline contour-based image computing over several months’ worth of data will be presented showing some of the benefits of integrating edge computing solutions in wafer fab production flow.

Proceedings Article | 26 May 2022 Presentation + Paper

Enabling on-device and target-free overlay measurement from CD-SEM contours

Thibaut Bourguignon, Régis Bouyssou, Jonathan Pradelles, Sébastien Bérard-Bergery, Bertrand Le-Gratiet, Romain Bange, Nivea Schuch, Thiago Figueiro, Nicolas Possémé

Proceedings Volume 12053, 120530C (2022) https://doi.org/10.1117/12.2613327

KEYWORDS: Overlay metrology, Scanning electron microscopy, Metrology, Image processing, Algorithm development, Feature extraction, Semiconducting wafers

Read Abstract +

Overlay is a critical parameter for any semi-conductor foundry, with a direct impact on the fabrication yield, on the quality, and on the performances of the product. Being able to full the overlay constraints has also a direct in influence on the capacity to scale down and to integrate vertically. In addition, the shift of semiconductor applications into more demanding markets such as spatial and automotive leads to higher specifications for the process control. In the semiconductor manufacturing, the overlay is usually measured optically using dedicated targets in the scribe lines. However, targets differ from the product by their dimensions of an order of magnitude larger and by their position up to a few millimeters far from it. This can lead to residual errors and mismatches in the correction sent to the scanner, thus lowering the fabrication yield and the global product quality. For years, many SEM in-device overlay techniques have been published, however they are generally related to new generation of SEM imaging and metrology equipment and require a new dedicated target. In our case, the ambition is to extend the usage of our current CD-SEM tool park. To do so, an on-device and target-free overlay measurement process has been developed. It is based on sub-pixel contour extractions from CD-SEM images and on the use of the design. From a single image, contours of the two layers of interest are extracted from the SEM image and a custom algorithm calculates the overlay as a difference of the realigned design centroids. This dedicated algorithm allows extracting various overlay measurements from one image and enables a production friendly implementation. To evaluate the performances of this method, it has been applied on the patterns of a SRAM with scanner-programmed overlay. The measurements are compared to the conventional optical measurements. On a basis of thousands on-device measurements, the developed method showed a promising 95% rate of successful measurements. Good correlation between the optical model and the CD-SEM measured overlay on the SRAM has been demonstrated, reaching a coefficient of correlation of 0.99 on a pattern where conventional centroid or CD based overlay are limited. Finally, the flexibility of the method to measure various patterns with an ease of recipe creation is shown. Contour-based metrology offers the capability to extract highly valuable information from SEM images while keeping the layers differentiation. The proposed measurement process, being automated and requiring relatively low human inputs is a promising solution for a SEM on device overlay metrology suitable in a high-volume manufacturing environment.

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years