A comparison was made between rapid-thermal processing and furnace processing with respect to gate oxidation, polysilicon sidewall oxidation, and junction activation anneal. NMOS and PMOS structures with N+ polysilicon gates, 6.5 nm gate oxide, and 70 nm source/drain junction depths were processed in parallel, using one-mask FET test structures to define MOSFETs with channel lengths down to 0.18 micrometers . Good NMOS device characteristics and low junction leakage were observed for all experimental combinations. Rapid-thermal and furnace oxidation exhibited similar gate-oxide breakdown characteristics.
A combination of metrology techniques was employed to fine tune the wavelength setting of a 248 nm excimer laser stepper to optimize performance. Scanning electron microscopy was used to document local resolution, proximity effects, and astigmatism, while GCA SMARTSETR and electrical resistance techniques were used to examine full field effects. Using the combined metrology methodologies, the authors documented the decrease in proximity effect, improvement in resolution, and increase in absolute lens distortion with negative shifts in laser wavelength setting, with a slight differential in the setting required to minimize horizontal versus vertical proximity effect and astigmatism. A wavelength offset of -2.3 angstroms from the nominal stepper setup wavelength was determined to be the best operating wavelength for these applications.
It is commonly recognized that there are three main causes of circuit yield losses: process related problems, design sensitivities, and point defects. Yield losses due to design sensitivity primarily occur during the early development phase of a VLSI circuit. Previous work in eliminating design sensitivities have concentrated on using statistical simulations which is computationally expensive for VLSI circuits with over million transistors. This paper describes an approach to detect design sensitivity using methods of pattern recognition and parsimonious hypothesis formation.
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