Mr. Yi-Shiang Chang Profile

Yi-Shiang Chang

Technical Manager at Powerchip Semiconductor Manufacturing Corp

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Publications (10)

Proceedings Article | 26 May 2022 Presentation + Paper

A novel approach of virtual etch target (VET) for efficient litho-to-etch pattern fidelity correction

Shr-Jia Chen, Yi-Shiang Chang, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 12052, 120520I (2022) https://doi.org/10.1117/12.2612298

KEYWORDS: Etching, Optical proximity correction, Logic, Lithography, Data modeling, Semiconducting wafers, Optical lithography, Double patterning technology

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For 28 nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as sub-resolution assist features (SRAF), litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning(SAQP), and source-mask optimization (SMO) are utilized for the low k1 factor lithography processes. The litho-to-etch pattern fidelity is extremely critical since a slight lithography pattern weakness (ex: photoresist (PR) thickness loss, profile roughness ...) may be worsened after etch process due to the pattern loading effect, which will then induce physical defects that affect the final electrical performance. Rigorous lithography simulation can provide a reference of pattern weaknesses to modify mask layouts; but it is incapable of full-field mask data preparation. The post-etch critical dimensions (CDs) with a high accuracy optical proximity correction (OPC) model has become an important component; but it requires massive wafer data of post-litho and post-etch CDs, and will increase the runtime of the OPC flow for OPC modelers. In our previous submission [1-2], we had brought forth an algorithm that utilizes multi-intensity levels from conventional aerial image simulations to assess the physical profile through lithography to etch steps, and proposed a novel litho-etch correction method without suffering the lithography process window of SADP process. In this paper, we have improved this methodology and introduced a new approach of virtual etch target (VET) with virtual etch target threshold to assess post-etch CDs for various applications of memory patterning (dense features by SADP or SAQP process) and logic patterning (random features of lines, trenches and holes) more efficiently. The results not only matched post-etch wafer data, but also agreed with post-etch process window. Furthermore, this methodology can be utilized in generic OPC and post-OPC verification procedures to improve final pattern fidelity for logic and memory products.

Proceedings Article | 27 March 2017 Presentation + Paper

A novel methodology for litho-to-etch pattern fidelity correction for SADP process

Shr-Jia Chen, Yu-Cheng Chang, Arthur Lin, Yi-Shiang Chang, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 10146, 101460N (2017) https://doi.org/10.1117/12.2258201

KEYWORDS: Lithography, Photoresist materials, Etching, Optical proximity correction, Resolution enhancement technologies, Photomasks, Semiconductors, Source mask optimization, Double patterning technology, Semiconducting wafers, Radon, Computer simulations

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Proceedings Article | 31 March 2014 Paper

Study of the pattern aware OPC

Shin-Shing Yeh, Alan Zhu, James Chen, Bayram Yenikaya, Yi-Shiang Chang, Chia-Chi Lin

Proceedings Volume 9052, 90521Y (2014) https://doi.org/10.1117/12.2046059

KEYWORDS: Optical proximity correction, Nanoimprint lithography, Resolution enhancement technologies, Control systems, Logic devices, Sensors, Lithography, Image quality, Metals, Process control

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Proceedings Article | 29 March 2013 Paper

Capability study and challenges to sub-2x nm node contact hole patterning

Wan-Lin Kuo, Ya-Ting Chan, Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, Ming-Chien Chiu, Chun-Hsun Chen, Hung-Ming Wu, Mao-Hsing Chiu

Proceedings Volume 8682, 86821G (2013) https://doi.org/10.1117/12.2011434

KEYWORDS: Etching, Chemical reactions, Scanning electron microscopy, Optical lithography, Image processing, Double patterning technology, Photoresist processing, Lithography, Photomasks, Process control

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Proceedings Article | 16 April 2011 Paper

Process capability of implementing ArF negative resist into production

Meng-Feng Tsai, Yang-Liang Li, Chan-Tsun Wu, Yi-Shiang Chang, Chia-Chi Lin

Proceedings Volume 7972, 79721B (2011) https://doi.org/10.1117/12.879316

KEYWORDS: Photomasks, Photoresist processing, Double patterning technology, Semiconducting wafers, Lithography, Printing, Etching, Critical dimension metrology, Line width roughness, Optical alignment

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Proceedings Article | 23 March 2011 Paper

A simple method of source optimization for advanced NAND FLASH process

Yi-Shiang Chang, Satoshi Ogasawara, Koichi Fujii, Shigeru Hirukawa, Motokatsu Imai, Wan-Lin Kuo, Chia-Chi Lin

Proceedings Volume 7973, 79731Z (2011) https://doi.org/10.1117/12.878887

KEYWORDS: Seaborgium, Light sources, Optical lithography, Imaging systems, Excel, Photomasks, Source mask optimization, Lithography, Lithographic illumination, Logic

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Proceedings Article | 3 April 2010 Paper

Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

Yi-Shiang Chang, Jason Sweis, Jun-Cheng Lai, Chia-Chi Lin, Jonathan Yu

Proceedings Volume 7637, 76371N (2010) https://doi.org/10.1117/12.845831

KEYWORDS: Photomasks, Double patterning technology, Metals, Electronic design automation, Lithography, Optical proximity correction, Computer simulations, Electron beam lithography, Etching, Manufacturing

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Proceedings Article | 23 March 2009 Paper

Alignment method of self-aligned double patterning process

Meng-Feng Tsai, Jun-Cheng Lai, Yi-Shiang Chang, Chia-Chi Lin

Proceedings Volume 7272, 72721Q (2009) https://doi.org/10.1117/12.813641

KEYWORDS: Optical alignment, Overlay metrology, Signal processing, Double patterning technology, Photomasks, Etching, Optical lithography, Semiconducting wafers, Manufacturing, Scanners

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Proceedings Article | 16 March 2009 Paper

Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

Yi-Shiang Chang, Meng-Feng Tsai, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 7274, 72743E (2009) https://doi.org/10.1117/12.814000

KEYWORDS: Photomasks, Double patterning technology, Etching, Lithography, Semiconducting wafers, Manufacturing, Electron beam lithography, Bridges, Optical alignment, Scanners

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Proceedings Article | 4 December 2008 Paper

Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

M. C. Chiu, Benjamin Szu-Min Lin, M. F. Tsai, Y. S. Chang, M. H. Yeh, T. H. Ying, Chris Ngai, Jaklyn Jin, Stephen Yuen, Sem Huang, Yongmei Chen, Liyan Miao, Kevin Tai, Amiad Conley, Ian Liu

Proceedings Volume 7140, 714021 (2008) https://doi.org/10.1117/12.804685

KEYWORDS: Etching, Double patterning technology, Lithography, Optical lithography, Line width roughness, Manufacturing, Scanners, Semiconducting wafers, Line edge roughness, 193nm lithography

Read Abstract +

High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.

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