For advanced technology nodes, it’s critical to address yield issues caused by process specific layout patterns with limited process window. RETs such as Model-Based Sub-Resolution Assist Feature (MB-SRAF) are introduced to guarantee high lithographic margin, but these techniques come with long runtime, especially when applied full-chip. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process.
In this paper, we introduce a flow that applies advanced RET such as MBSRAF or specific local corrections to layouts with critical and yield limiting patterns. We also introduce in-process pattern match based on Cadence topological Squish pattern. Overall, this new flow of Pattern-Aware OPC (PA-OPC) achieves better margin for hotspots, without sacrificing turnaround time and is able to handle more complex patterns and environment than traditional methods. We demonstrate the benefit of the new flow with fine-grained process window control over different patterns.
In this paper we introduce an inverse lithography technology (ILT) solution that provides masks with perfect symmetry and minimal complexity. In this solution we divide the ILT problem into three steps and strictly maintain symmetry in each of these steps. First, we optimize an ideal grayscale mask. Second, we seed this ideal mask with polygons. Finally, we grow these seeds in a separate optimization flow. The final mask perfectly maintains the symmetry properties of the illumination source. To the best of our knowledge, this is the first ILT solution that can be used on the original design hierarchy on a full chip scale.
It’s critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.
As the feature sizes printed with optical lithography get smaller, Kirchhoff’s thin mask approximation used in full chip optical proximity corrections (OPC) fails to yield acceptable accuracy due to thick mask diffraction effects. One of the most observed effects of the thick mask diffraction is that it creates different focus shift for different patterns. When Bossung curves (CD plots with respect to defocus) of various patterns are observed from rigorous simulations and from actual wafer data one can notice that each pattern has a different best focus. Depending on the pattern, Bossung curves can be offset in either positive or negative direction. This significantly reduces the common depth of focus (DOF) for which all patterns print with acceptable fidelity. Even though each pattern by itself may have an acceptable DOF, the common DOF may not be acceptable. Several extensions to the thin mask approximation have been developed that model this behavior accurately, such as boundary layer approximations and domain decomposition methods. These methods provide a more accurate approximation than the thin mask model while still being computationally efficient to be useful for full chip OPC. Even though these approximations model and predict the focus shift accurately, to the best knowledge of the authors no method has been published to use these modeling capabilities to automatically fix this focus shift during OPC. In this paper we provide an optimization method to significantly reduce focus shift due to 3D mask effects during OPC. We show that our 3D mask model can predict this focus shift fairly accurately and we also demonstrate how we use this model in OPC to reduce focus shift, which significantly improves the common DOF for the entire layout.
In a recent paper15, we presented a novel method for fully automated model-based generation and optimization
of sub-resolution assist features which, when placed on a contact layer photomask, minimize the variations in the printed
pattern with respect to focus change. Here we extend that methodology to improve the contrast of the light intensity in
addition to minimizing variations caused by focus change.
We present a model-based method of generating and optimizing sub-resolution assist features. Assist feature
generation is based on a focus sensitivity map derived from a cost function that minimizes the variations in the printed
pattern with respect to focus change. We also demonstrate a method to generate mask-friendly SRAF polygons from the
focus sensitivity map. After model-based placement, assist features and the main polygons are optimized together by
moving their edge segments. One of the optimization goals is that side-lobes and assist features should not print. This is
enforced by computing image on a two dimensional grid. We demonstrate the process window improvement for a
contact layer example.
We present a method for optimizing a free-form illuminator implemented using a diffractive optical element (DOE). The
method, which co-optimizes the source and mask taking entire images of circuit clips into account, improves the
common process-window and 2-D image fidelity. We compare process-windows for optimized standard and free-form
DOE illuminations for arrays and random placements of contact holes at the 45 nm and 32 nm nodes. Source-mask cooptimization
leads to a better-performing source compared to source-only optimization. We quantify the effect of typical
DOE manufacturing defects on lithography performance in terms of NILS and common process-window.
We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive
images of 1/4-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces.
We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling
the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows
that overlay and etch bias are the most significant contributors to the variability of spaces. 3σ[space-width] = 17% and
11% of nominal space can be achieved for 3σ[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array
printed using NA=0.93.
We present a necessary condition for an arbitrary 2-dimensional pattern to be printable by optical projection lithography.
We call a pattern printable if it satisfies a given set of edge-placement tolerances for a given lithography model and
process-window. The test can be made specific to a lithography model, or it can be made generic for a wavelength and
numerical aperture. In the generic form, if a pattern is found to be not printable, the conclusion is valid for all RET
technologies except for non-linear techniques such as litho-etch-litho-etch double-patterning and multi-photon
lithography. The test determines printability of a target layout without applying RET/OPC.
We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive
images of 1/4-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces.
We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling
the space-width to ±10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows
that overlay and etch bias are the most significant contributors to the variability of spaces. 3&sgr;[space-width] = 17% and
11% of nominal space can be achieved for 3&sgr;[Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array
printed using NA=0.93.
We optimize a continuous-tone photomask to meet a set of edge-placement tolerances and 2-D image fidelity
requirements, for a set of dose and defocus values. The resulting continuous tone mask, although not realizable,
indicates where to place assist features and their polarity. This algorithm derives assist features from first principles:
when the mask is optimized for best focus, the optimal continuous-tone photomask does not have any features that
resemble assist features. When the mask is optimized for best focus and a defocus condition, the optimal continuous-tone
photomask spontaneously grows assist features. The continuous-tone photomask also has features that can be
identified as phase windows. Polygonal, quantized assist features are extracted from the optimal continuous-tone photomask.
In optical proximity correction, edges of polygons are segmented, and segments are independently moved to meet line-width or edge placement goals. The purpose of segmenting edges is to increase the degrees of freedom in proximity correction. Segmentation is usually performed according to predetermined, geometrical rules. Heuristic, model-based segmentation algorithms have been presented in the literature. We show that there is an optimal and unique way of segmenting polygon edges.
We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.
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