An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25μm silicon-on-sapphire CMOS with
a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60μm. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore
the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation
design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the
divider speed.
A single-FET active balun has been developed with a phase imbalance of less than ±1.5° and amplitude imbalance less
than ±0.6dB from 4 to 8 GHz using 0.25μm silicon-on-sapphire CMOS. The source terminal of the transistor has been
compensated with a shunt capacitance to ground and increased value for the source resistance. The compensation
network has improved the phase imbalance by 29° at 8 GHz. The circuit dissipates 15mW and is 260×300μm including
AC coupling capacitors.
Butler matrices can be used in antenna beam-forming networks to provide a linear phase distribution across the elements of an array. The development of an 8 to 18GHz micro-strip implementation of a 4-input 4-ouput Butler matrix is described. The designed Butler matrix uses March hybrids, Schiffman phase shifters and wire-bond crossovers integrated on a single 60mm x 70mm alumina substrate.
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