A 6-18.5 GHz dynamic frequency divider in 0.25µm SOI CMOS

Leigh Milner

doi:10.1117/12.758883

21 December 2007 A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS

Leigh Milner

Proceedings Volume 6798, Microelectronics: Design, Technology, and Packaging III; 679806 (2007) https://doi.org/10.1117/12.758883
Event: SPIE Microelectronics, MEMS, and Nanotechnology, 2007, Canberra, ACT, Australia

Abstract

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25μm silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60μm. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Citation Download Citation

Leigh Milner "A 6-18.5 GHz dynamic frequency divider in 0.25μm SOI CMOS", Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 679806 (21 December 2007); https://doi.org/10.1117/12.758883

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available