KEYWORDS: Sensors, Charge-coupled devices, Analog electronics, X-rays, Analog to digital converters, CCD image sensors, Power consumption, X-ray imaging, Prototyping, Iron
The Advanced x-ray Imaging Satellite (AXIS) is a NASA probe class mission concept designed to deliver arcsecond resolution with an effective area ten times that of Chandra (at launch). The AXIS focal plane features an MIT Lincoln Laboratory (MIT-LL) x-ray charge-coupled device (CCD) detector working in conjunction with an application specific integrated circuit (ASIC), denoted the Multi-Channel Readout Chip (MCRC). While this readout ASIC targets the AXIS mission, it is applicable to a range of potential x-ray missions with comparable readout requirements. Designed by the x-ray astronomy and Observational Cosmology (XOC) group at Stanford University, the MCRC ASIC prototype (MCRC-V1.0) uses a 350nm technology node and provides 8 channels of high speed, low noise, low power consumption readout electronics. Each channel implements a current source to bias the detector output driver, a preamplifier to provide gain, and an output buffer to interface directly to an analog-to-digital (ADC) converter. The MCRC-V1 ASIC exhibits comparable performance to our best discrete electronics implementations, but with ten times less power consumption and a fraction of the footprint area. In a total ionizing dose (TID) test, the chip demonstrated a radiation hardness equal or greater to 25krad, confirming the suitability of the process technology and layout techniques used in its design. The next iteration of the ASIC (MCRC-V2) will expand the channel count and extend the interfaces to external circuits, advancing its readiness as a readout-on-a-chip solution for next generation x-ray CCD-like detectors. This paper summarizes our most recent characterization efforts, including the TID radiation campaign and results from the first operation of the MCRC ASIC in combination with a representative MIT-LL CCD.
Future strategic x-ray astronomy missions will require unprecedentedly sensitive wide-field imagers providing high frame rates, low readout noise and excellent soft energy response. To meet these needs, our team is employing a multi-pronged approach to advance several key areas of technology. Our first focus is on advanced readout electronics, specifically integrated electronics, where we are collaborating on the VERITAS readout chip for the Athena Wide Field Imager, and have developed the Multi-Channel Readout Chip (MCRC), which enables fast readout and high frame rates for MIT-LL JFET (junction field effect transistor) CCDs. Second, we are contributing to novel detector development, specifically the SiSeRO (Single electron Sensitive Read Out) devices fabricated at MIT Lincoln Laboratory, and their advanced readout, to achieve sub-electron noise performance. Hardware components set the stage for performance, but their efficient utilization relies on software and algorithms for signal and event processing. Our group is developing digital waveform filtering and AI methods to augment detector performance, including enhanced particle background screening and improved event characterization. All of these efforts make use of an efficient, new x-ray beamline facility at Stanford, where components and concepts can be tested and characterized.
Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detection technology that can, in principle, provide significantly greater responsivity and improved noise performance than traditional charge coupled device (CCD) readout circuitry. The SiSeRO, developed by MIT Lincoln Laboratory, uses a p-MOSFET transistor with a depleted back-gate region under the transistor channel; as charge is transferred into the back gate region, the transistor current is modulated. With our first generation SiSeRO devices, we previously achieved a responsivity of around 800pA per electron, an equivalent noise charge (ENC) of 4.5 electrons root mean square (RMS), and a full width at half maximum (FWHM) spectral resolution of 130eV at 5.9keV, at a readout speed of 625Kpixel/s and for a detector temperature of 250K. Importantly, since the charge signal remains unaffected by the SiSeRO readout process, we have also been able to implement Repetitive Non-Destructive Readout (RNDR), achieving an improved ENC performance. In this paper, we demonstrate sub-electron noise sensitivity with these devices, utilizing an enhanced test setup optimized for RNDR measurements, with excellent temperature control, improved readout circuitry, and advanced digital filtering techniques. We are currently fabricating new SiSeRO detectors with more sensitive and RNDR-optimized amplifier designs, which will help mature the SiSeRO technology in the future and eventually lead to the pathway to develop active pixel sensor (APS) arrays using sensitive SiSeRO amplifiers on each pixel. Active pixel devices with sub-electron sensitivity and fast readout present an exciting option for next generation, large area astronomical x-ray telescopes requiring fast, low-noise megapixel imagers.
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