Model based hint for litho hotspot fixing beyond 20nm node

Jae-Hyun Kang; Byung-Moo Kim; Naya Ha; Hung bok Choi; Kee sup Kim; Sarah Mohamed; Kareem Madkour; Wael ElManhawy; Evan Lee; Jean-Marie Brunet; Joe Kwan

doi:10.1117/12.2011619

29 March 2013 Model based hint for litho hotspot fixing beyond 20nm node

Jae-Hyun Kang, Byung-Moo Kim, Naya Ha, Hung bok Choi , Kee sup Kim , Sarah Mohamed, Kareem Madkour, Wael ElManhawy, Evan Lee, Jean-Marie Brunet, Joe Kwan

Author Affiliations +

Proceedings Volume 8684, Design for Manufacturability through Design-Process Integration VII; 86840N (2013) https://doi.org/10.1117/12.2011619
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.

Citation Download Citation

Jae-Hyun Kang, Byung-Moo Kim, Naya Ha, Hung bok Choi , Kee sup Kim , Sarah Mohamed, Kareem Madkour, Wael ElManhawy, Evan Lee, Jean-Marie Brunet, and Joe Kwan "Model based hint for litho hotspot fixing beyond 20nm node", Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840N (29 March 2013); https://doi.org/10.1117/12.2011619

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