Paper
21 March 2012 Pattern scaling with directed self assembly through lithography and etch process integration
Benjamen Rathsack, Mark Somervell, Josh Hooge, Makoto Muramatsu, Keiji Tanouchi, Takahiro Kitano, Eiichi Nishimura, Koichi Yatsuda, Seiji Nagahara, Iwaki Hiroyuki, Keiji Akai, Takashi Hayakawa
Author Affiliations +
Abstract
Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron (TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with the long term goal of robust manufacturability. This paper provides a wide range of DSA demonstrations to accommodate different device applications. In collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA (poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity (CDU) of 0.9 nm (3s) and contact edge roughness (CER) of 0.8 nm. To generate higher resolution beyond a PS-b-PMMA system, a high chi material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Benjamen Rathsack, Mark Somervell, Josh Hooge, Makoto Muramatsu, Keiji Tanouchi, Takahiro Kitano, Eiichi Nishimura, Koichi Yatsuda, Seiji Nagahara, Iwaki Hiroyuki, Keiji Akai, and Takashi Hayakawa "Pattern scaling with directed self assembly through lithography and etch process integration", Proc. SPIE 8323, Alternative Lithographic Technologies IV, 83230B (21 March 2012); https://doi.org/10.1117/12.916311
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CITATIONS
Cited by 34 scholarly publications and 4 patents.
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KEYWORDS
Directed self assembly

Etching

Semiconducting wafers

Line edge roughness

Picosecond phenomena

Lithography

Polymers

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