Poster
10 April 2024 Layout to SEM: hotspot prediction via SEM image synthesis
Jaehoon Kim, Jaekyung Lim, Tae-Yeon Kim, Yunhyoung Nam, Do-Nyun Kim
Author Affiliations +
Conference Poster
Abstract
Since the rise of transistors and integrated circuits, the semiconductor industry has seen rapid advancements, leading to today's microchips containing hundreds of millions of transistors. A pressing challenge in this industry is the emergence of defects, termed "hotspots," during the manufacturing process, affecting chip performance and reliability. In this study, we introduce a deep learning model that predicts hotspots during the design stage. To predict hotspot, our proposed framework generates Scanning Electron Microscopy (SEM) images from layout by combining segmentation and image-translation network. This model outperformed existing baseline models when tested on real industrial datasets, promising to refine the semiconductor design workflow.
© (2024) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jaehoon Kim, Jaekyung Lim, Tae-Yeon Kim, Yunhyoung Nam, and Do-Nyun Kim "Layout to SEM: hotspot prediction via SEM image synthesis", Proc. SPIE 12955, Metrology, Inspection, and Process Control XXXVIII, 1295528 (10 April 2024); https://doi.org/10.1117/12.3009864
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KEYWORDS
Scanning electron microscopy

Semiconductors

Industry

Manufacturing

Data modeling

Performance modeling

Process modeling

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