A wideband signal processor based on a common module concept is presented that has applications to both radar and signal-intercept applications. This processor is suitable for the coherent pulse compression of wideband radar signals, the intercept/characterization of spread-spectrum radar and communication signals, and the generation of the radar ambiguity function. This paper describes the theory, operation, and application of the processor, which is composed of several modules, including a 1-GHz-bandwidth wideband correlator module, a 200-MHz four-product correlator module, a radio frequency receiver and waveform/transmitter module, and a digital processing and operator interface module for use in field demonstrations.

A mixed analog/digital integrated circuit which performs the post optical signal processing functions for an acousto-optic channelizer system is presented. The signal analysis and additional specialized functions on this circuit provide a complete solution to the processing needs of highly compact channelizer systems. Functionality of the 27-channel postoptical processor is achieved with a single design pass and wafer run. Wafers probed with automatic test equipment, based on a several-thousand vector long functional probe program, yielded an average of 44 percent which is considered to be a good yield for a die of this complexity and size. It is concluded that the integration of all necessary functions makes it possible to reduce channelizer system weight, volume, and power consumption by several orders of magnitude.

Artificial neural networks(ANN5) and their ability to model and control dynamical systems for smart structures including sensors actuators and plants are being considered in our lab. Both linear and non-linear systems have been successfully modeled. We are presently working on two diverse regimes smart mechanical systems and smart electromagnetic systems. In order to better understand neural controllers as used in the smart electromagnetic structures we have directed our study of ANNs toward understanding the ability of the network to approximate system responses. We are training networks to mimic the desired output of the system. The damped sinusoid was chosen as the model and was approximated using a Jordan-like 8 iterative network. The results to date indicate that the ANNs can easily mimic these systemsthe question is whether the mechanism that the network applies can be related to the mechanisms that we understand for classical analysis. Sensor preprocessing represents a significant element in the smart material and structure concept. We are looking at certain network architectures as sensor preprocessors. Results from both these areas will be presented in this paper.

Signal processing requirements and techniques for a class of optical sensors, based on continuous wavelength encoding of sensed data, are discussed. The sensors function as narrow-band transmission filters with the wavelength controlled by the sensed parameter. The signal processor must determine the wavelength of the narrow band peak in real time with an accuracy of at least 0.1 percent of full scale. The electrooptic techniques presently used to detect and process these signals are described along with the associated benefits and limitations. The results from testing these techniques are presented and compared. Several innovative techniques with the potential for reducing the size and weight of the processing elements are proposed. Results from computer simulations of the proposed techniques are presented. Sensor and signal-conditioning multiplexing methods for these sensor systems and the impact on system operation are discussed. An analysis of the signal-processing techniques with respect to throughput, accuracy, cost, weight, and impact on system operation is presented.

Acoustooptic channelized receivers employing incoherent, time-integrating detection are limited to a pulse time-of-arrival (TOA) resolution equal to the photodetector integration time. A novel method is shown for utilizing two synchronous channelizers to achieve fine-grain TOA resolution within an integration period. The addition of a third channelizer is shown to yield pulse width information.

For analog signal applications, lithium niobate Mach-Zehnder modulators are biased at the V pi/2 operating point to achieve maximum dynamic range and minimum signal distortion. Even a slight deviation from this optimum bias point causes severe reduction in the available dynamic range. Because of device instabilities, the bias voltage for the optimum operating point can drift with time-requiring constant readjustments. The automatic bias controller described in this paper automatically generates the desired bias voltage to maintain the optimum operating point - even in the presence of modulator drift. The bias controller operates with only one optical tap from the modulator output and is insensitive to variations in the absolute-optical-intensity level.

A modified real-time holographic technique for obtaining high fidelity integration of coherent or incoherent signals is described. The technique maintains the sensitivity, resolution, and incoherent addressability of a photorefractive incoherent to coherent optical converter and resolves the conflict between uniformity and dynamic range. The response of the resulting optical integrator is characterized in terms of the transfer function, dynamic range, and temporal tunability.

A new optical approach capable of providing simultaneous estimates of azimuth and elevation is presented. It is shown how acoustic and optical methods can be combined to reconstruct the far field of a 2D array. Particular attention is given to the basic theory of, and a quantitative transfer function for, the optical beamformer.

Consideration is given to an advanced version of the acoustooptic time-and-space integrating (TSI) approach to real-time SAR imaging for severe power and size constraints applications. The concept incorporates electronic programmability and has the flexibility to compensate for the anomalies of the SAR imaging problem in a dynamically changing data collection scenario. Particular attention is given to a computationally intensive spotlight mode and real-time acoustooptic programmable imaging and display for SAR. It is concluded that all of the electronically programmed signals are straightforward to calculate and can be handled by standard digital processors, at real-time rates without taxing their capabilities. The effective distribution of the computational load between optics and electronics indicates that this SAR architecture is potentially compact and has low power requirements for both the electronic and optical portions of the processor.

The dynamic range consideration of complex integer computations in a complex residue number system (CRNS) normally necessitates scaling. As the scaling factor increases so does inaccuracy of the CRNS computation. The dynamic range may be increased only at the expense of accuracy. Algebraic integer RNSs (AIRNSs) and separable moduli RNSs (SMRNSs) have been studied because of their potential for reducing the scaling requirement . To further understand AIRNSs and SMRNSs a general conversion procedure between the two number systems has been coded and used to draw some preliminary conclusions about scaling. 1. 0

Bragg cells fabricated from mercurous bromide, Hg2Br2, offer the possibility of long time-delay signal processing in a compact package. Crystal growth and fabrication techniques provide the key to exploiting this material for practical signal-processing devices. Bragg cells from Hg2Br2 are fabricated and tested that are approximately 5.5-cm long, which corresponds to 200 microsec delay time.

A new type of memory device is presented which takes advantage of the volume of a storage material in order to achieve extremely high information density and capacity. The unique properties of two-photon materials allows for reading and writing to any localized region throughout the volume of material. In addition to the high capacity the 2-photon 3-D memory system has been designed to access up to 106 bits in a single clock cycle. This large parallelism combined with an access time of 1/1 sec gives a memory bandwidth of 1012 bits/sec. It is shown that this value of memory bandwidth far exceeds that available from current memory systems and therefore is well-suited for the demands of current and future supercomputing systems. 1.

Use of the interferometric spectrum analyzer as an RF channelized receiver requires careful optimization of optical beam apodization to achieve an acceptable channel bandshape and to suppress spurious modulation produced by the self-interference of optical local oscillators which can limit dynamic range. Design techniques are shown for proper optimization and factors which limit performance in practical systems are discussed. It is shown that reference self-interference spurs can be controlled if the reference Bragg cell has a time-bandwidth product which significantly exceeds the number of channels. Other spurious suppression techniques are considered as well. Non-Gaussian apodization is shown to result in an improved bandshape for channelized receiver applications.

A polynomial evaluator utilizing a pipelined architecture has been constructed and tested. Some notable features of this processor are its unusual design its speed in polynomial evaluation and its ability to rapidly compute the zeros of polynomials. This optical computer utilizes sequential processing by seven electrooptic gratings which perform alternate addition and multiplication functions in the pipeline. Its performance as a square-root processor and as a cubic polynomial evaluator are stressed. Characterization measurements upon the individual gratings and upon the processor as a system are presented. 1.

Narrow spectral width microwave and millimeter-wave signals were generated by using optical heterodyne and optical injection locking techniques. The phase of the signal was electrooptically controlled using integrated optical Ti:LiNbO3 waveguide modulator.

The fabrication of ferroelectric-liquid-crystal (FLC) light modulators directly atop silicon integrated-circuit (IC) active backplanes makes possible a new family of spatial light modulators (SLMs). Both FLC and IC characteristics play a role in determining the hybrid SLM''s performance capabilities. Total element number is limited to about 1000 x 1000 by current VLSI resolution and die-size constraints. SLM frame times are limited to about 100 microns by FLC response times for element numbers below about 256 x 256 and by IC power dissipation and electronic interconnect bandwidth above that size. Corrugations on the IC surface produced by the VLSI processing can cause severe intrapixel optical wavefront nonuniformity, but elements on the prototypes whose reflectors are restricted to circuitry-free regions have peak-to-valley roughness of less than 0.1 micron across a single pixel. Standard silicon foundry IC dies yielded SLMs flat to about a quarter-wave at 546 nm across a 5-mm aperture.

Two variants of a fiber-optical crossbar switch based on the magnetooptical spatial light modulator (MOSLM) have been developed for the purpose of connecting N inputs with M outputs with the arbitrary reconfiguration network. The 2D MOSLM uses Bi-substituted iron garnet film and consists of 128 x 128 elements. In the first variant the MOSLM is used as a multichannel array of light-beam shutters with vector-matrix multiplicator architecture for a small (less than 10) number of optical channels. In the second variant, the MOSLM is used as a multichannel light deflector for a high (10 and more) number of optical channels and appeared to be more effective. Experiments show that switching times are in the range from 0.1 to 10 microsec, while the best results were obtained in the case of films with pronounced orthorhombic anisotropy.

The design for two high fill-factor CCD arrays for optical signal processing applications is described. The imaging registers have 1024 x 1024 and 512 x 512 pixels and achieve virtually 100 percent optical fill factor through the use of substrate thinning and back illumination. High frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports resulting in reduced readout frequency. On-chip correlated double sampling amplifiers are implemented to reduce the readout noise and simplify off-chip analog signal processing. Both chips include antiblooming drain structures and ESD protection circuits.

Recent advances in optoelectronic devices are reviewed focusing on semiconductor lasers, optical amplifiers, and both monolithic and hybrid optoelectronic integrated circuits. Problems discussed include discrete optoelectronic components, optoelectronic integrated circuits, and passive components made of III-V compounds and hybrid integration of optoelectronic devices and other guiding media.

Optical interconnects are being considered for the high speed distribution of multiplexed control signals in GaAs MMIC-based phased array antennas. This paper describes the performance of a hybrid GaAs optoelectronic integrated circuit (OEIC), along with a description of its design and fabrication. The OEIC converts a 16-bit serial optical input to a 16 parallel line electrical output using an on-board 1:16 demultiplexer and operates at data rates as high as 305 Mbps. The performance characteristics as well as potential applications of the device are presented.

Current research on optoeletronics is reviewed with particular attention given to thin film devices from II-VI and III-V compound semiconductors. Major achievements made since 1988 include development of world-class growth facilities for ZnSe and III-V compound semiconductor epitaxial layers and processing of these materials into devices with world-record performance characteristics.

Consideration is given to a multichip interconnect approach representing a new packaging technique that eliminates drawbacks of a conventional hybrid circuit and avoids difficult technologies required for a fully monolithic circuit. The process is considered to be simple, and mass production is considered to be feasible with some automation. Since no constraints are imposed on the chips used, any commercially available device or circuits can be packaged using this technique.

A simple and efficient board-to-board optical interconnection consisting of a laser, two lenses and a detector is constructed, which demonstrates the direct free-space interconnection of GaAs digital circuits. The link is operated at clock rates up to 1 GHz, and no external laser driver, detector preamplifier or other interface circuitry is required because of the high efficiency of the interconnection. A differential electrical-to-electrical current efficiency is measured as high as 19 percent. The use of prealigned optical modules promises increased tolerance to misalignments.

A novel optical interconnect technology is presented. It combines single mode waveguides with multiplexed volume waveguide holograms to provide a highly parallel, very wide bandwidth system for VLSI, computer board or backplane computer interconects. Interconnect density and system performance are analyzed. Experimental results of a 1-to-20 waveguide interconnection are presented.

A technique is described for packaging commercial lasers, ELEDs, and detectors for military environments with a wide range of temperatures. Laser welding and gradient-index lenses are combined in the packaging design, and stable coupling efficiency is achieved by utilizing both pigtailed single-mode fiber packages and SMA connectorized multimode fiber packages. The coupling efficiency is demonstrated to be high, and packages are described which are suitable for commercial devices with diameters of 9 and 5.6 mm.

Laser-diode arrays were optically coupled to single-mode uptapered and single-mode cleaved fibers through a single lens. Coupling efficiencies ranged from 34 to 9 percent for five-element-edge-emitting arrays having 254-micron laser spacing and from 31 to 7 percent for arrays having 350-micron laser spacing. The number of laser elements that could be coupled through the lens was limited by its numerical aperture. Optical crosstalk between separately addressed laser elements was less than -50 dB. Uptapered fibers showed a fivefold relaxation of the translational alignment tolerance compared to cleaved fibers. When surface-emitting lasers are used the numerical aperture limitation of the lens allows many more elements to be coupled. A proposed example is shown of a surface-emitting array coupled to 17 fibers through one lens.

The use of bipolar GaAs ICs is evaluated with respect to the AN/APS-137 Inverse Synthetic Aperture Radar (ISAR) system on the basis of power and size requirements and resolution quality. System upgrades include a software change and other modifications in the receiver weapon-replaceable assembly (WRA). A block diagram of the receiver WRA is given which describes the modified circuitry after the insertion of GaAs ICs. A 250-MHz technology is required to achieve a 200 MHz sampling rate with 80-percent reliability derating, and the GaAs satisfies this requirement. The IC designs are described with particular attention given to the data buffer and delay generator and related operational requirements. It is shown that the two GaAs ASICs using the Standard Gate structure can provide the resolution improvements required for the AN/APS-137 radar ISAR range.

Results are presented of the feasibility study for the GaAs DSP implementation and are compared with previously reported designs. This processor will be incorporated into an insertion module and demonstrates that GaAs DSP replacement modules, reduced to multichip package size, can achieve critical signal processing functions in a typical RF seeker system. Architectural features are offered that effectively make it a high-speed MIMD processor with more than a ten-fold performance advantage over its silicon counterpart. This radar system design provides the compatibility to realize hundreds of megahertz of effective signal bandwidth and precision of performance required.

The procedure of the insertion of a digital GaAs radar signal processor (GRASP) technology into the E-2C airborne early warning system is described, with special attention given to the hardware technology and design considerations. Two subsystems will be included in the digital GRASP: the displaced phase center antenna and a skew Doppler processing function (which is a new algorithm that, when implemented, will replace the coherent integrator). The strategies used for implementing the digital signal processing algorithms in GaAs are presented.

A very-high-speed sensor processor subsystem (MSPS) is described in terms of its design, fabrication techniques, and applications to fielded military systems. Incorporated in the design are high-speed GaAs and Si integrated circuits and an algorithm for aided target recognition and multiple target tracking. The existing Mast Mounted Sight (MMS) system is described, and the MSPS system is described in detail to permit a comparison of the two system processors. The speed of the proposed system is 100 million instructions/s, and the system operates in parallel and offers 24-bit floating point multiplies and ALU operations and 16 bit integer multiplies internal with 24-bit integer operations and external memory access. The processor employs existing form factor, power supply, operational software, and interfaces, and can be operated at about the same cost with reduced operator workload.

The major design considerations encountered in adapting the DAP-510 processor with GaAs and the operational improvements of the GaAs high-speed parallel processor are presented. Studies indicate that the DAP-510 unit is capable of processing radio navigation signals in dense environments exceeding 100,000 pulses/sec. The processor comprises 1024 single-bit, concurrent processor elements arranged in a 32- by 32-element array. The processor memory is designed to have 65,536 bit planes of data memory and 1 Mbyte of instruction memory.

An advanced, low power, high performance GaAs standard cell library (SC10000) has been developed which is uniquely applicable to signal processing applications. The SC10000 library is based on source-coupled logic (SCL) in order to achieve good noise margin with small voltage swings and optimum speed-power product. The SCL design techniques can simplify complex logic to a single current tree, resulting in faster real-time arithmetic operations. In addition to low power cells, the SC10000 library contains very high performance cells such as input buffers, clock drivers, and flip-flops running at speeds up to 6.5 GHz. The library is supported by an advanced enhancement-depletion mode MESFET technology which has been built around the heart of a proven depletion mode technology. This advanced technology can easily support very large scale integrated circuits of 10000 gate complexity. Furthermore, the library is supported on several CAD/CAE systems to shorten the ASIC design cycle.

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

A library of custom macrocells has been designed for the implementation of high performance Gallium Arsenide (GaAs) digital integrated circuits in the AT performance and LSI functionality while minimizing power dissipation and area requirements. The entire library may be clocked up to 500 MHz with smaller cells, such as flip-flops, sustaining clock rates up to 2 GHz. The macrocells are designed around a SFL logic family which uses a 2.0 volt power supply. The cells in the library range in function from simple NOR, XOR, clock drivers and I/O buffers to higher function macrocells, such as, Booth multipliers, barrel shifters, ALU, adders, flip-flops and 4-bit up/down counters. Output buffers are designed to drive 50 ohm transmission lines with a 1.0 volt logic swing. An unloaded buffered 3-input NOR gate cell exhibits an average propagation delay of 115 ps per gate while dissipating only 1.5 mW of power for a speed-power product of 173 fJ. The unloaded delays are derated by 0.3 ps/fF load capacitance and 2 ps per fanout. The macrocells were designed for the AT enhancement/depletion mode process which has 1.0 micron gates and 2.0 micron design rules. This library has been used in circuits to provide a functional density of over 15,000 equivalent gates/sq cm. Current designs using this macrocell library include an 8x8 multiplier and a 16 tap transversal filter chip.

This paper discusses the features and function of three specific computer aided design tools contained in the Mayo Graphical Integrated Computer Aided Design (MagiCAD) system a complete electronic CAD software package optimized for the design and layout of semicustom (i. e. gate array) Gallium Arsenide (GaAs) integrated circuits. The first design tool the Layout Extractor processes data from placed and routed gate arrays. The Extractor verifies that the layout represents the original logic design and calculates the parasitic capacitance of the individual wiring segments in the logic nets after they have been routed. The capacitance information as calculated by the Layout Extractor is significant in GaAs work since the delay in signals traveling through the routing is often much greater than the delay of the signals traveling through the gates themselves. Once the capacitance data has been processed by the Layout Extractor it becomes available to the second CAD tool discussed here the MagiCAD timing simulation program Sting. Sting a digital event-driven simulator depends on user generation of C language-like behavioral models for all root nodes to be simulated. Through the use of delays calculated by the Extractor from the actual routing and input pin capacitances Sting assures that the entire chip design will operate correctly at the intended clock rate. The third design tool is a set of programs allowing simulation of the electromagnetic behavior of integrated circuit packages circuit

Advanced digital communication services11 such as Broadband ISDN High Definition Television (HDTV) and enhanced data networking are expected to require high bandwidth and fast reconfiguration time switching centers available in the 1990''s. Digital GaAs IC''s can allow the implementation of these switching centers providing these services efficiently and at a low cost. The low cost arises from the reduction in hardware power maintenance etc. when the switch is designed to operate at the incoming data rate instead of at a lower rate. In order to utilize the capacity of a high bandwidth data link time division multiplexing is employed. This is a technique where multiple digital signals are interleaved (bit byte or block) on one data link. Clearly it is advantageous to have a switch that not only has a large bandwidth but can reconfigure at the data rate so as to provide bit byte or block switching functions thus being compatible with many different transmission formats. We present an experimental Time/Space Division Switch System capable of operating at over 1 Gb/s. Both custom and commercial Gallium Arsenide (GaAs) devices are used in the design of the various system functional blocks. These functional blocks include a Time Slot Interchanger (TSI) Time Multiplexed Switch (TMS) TMS Controller Multiplexer and Demultiplexers. In addition to the system overview we discuss such issues as printed circuit board microwave interconnections and CAD tools for high speed

GaAs integrated circuit technology is being applied to improve the performance and functionality of the Digital Video Mapping System. A 400 MFLOP 32 bit floating point processor will be used to accelerate data and graphics processing algorithms. The GaAs processor will contain 4 circuit types interconnected using a thin film multilayer packaging technology. The processor clock rate is 200 MHz and the I/Os are at CMOS levels operating at less than 50MHz.

A high-speed communications chip set based on a 1500-gate structured cell gate array, designed specifically for interprocessor communications in multiprocessor environments has been developed. Needing a minimum of support logic, these three chips provide all link functions, including parallel/serial and serial/parallel conversion, data encoding/decoding, idle/quiet line detection, data clock phase recovery, and link error indicators. The link clock rate is 1 GHz, supporting a data rate of 800 megabit/second.

A high-speed GaAs transversal filter IC has been developed that contains in excess of 41,000 transistors which implements a finite impulse response filter for IR data stream SNR (S/N) enhancement in clutter rejection systems. The circuit contains an address controller in addition to a multiply/accumulate processor for interfacing with external memory and a register file for storing progammable filter coefficients (tap weights). Very-high-speed operation, as shown by a predicted clock rate of 160 MHz, is obtained through the utilization of a pipelined architecture and an advanced GaAs processing technology. The high-performance characteristics of this circuit permit it to be applied as a single serial processor to systems normally requiring parallel processing techniques.

To maximize the performance of digital gallium arsenide devices a full function must be implemented in a single device. One method to achieve this goal is to partition the function into smaller independent functions using using the residue number system. The residue number system is well suited to maximizing the performance of these devices specifically digital signal processing tasks such as finite impulse response (FIR) filters and fast Fourier transforms.

As associative memories begin playing an Increasingly Important role In the desIgn of hIgh-performance systems novel circuit desIgn and chip architecture approaches for these devices become crucial. Currently designed exclusively in silicon associative memory circuits have recently been introduced as commercial parts. While not as mature as silicon gallium arsenide (GaAs) may hold a key for providing several advantages over silicon in associative memory performance. This paper will address the technical issues surrounding the application of GaAs in the design of associative memory circuits. Several current silicon applications of associative memory will be described. An overview of some of the most recent circuit developments will be included along with a description of some of the prominent features of available associative memories. GaAs will then be introduced as a technology which holds certain key advantages over silicon. These features stand to dramatically improve the speed and processing capability of logic which is found in most associative memory. A novel GaAs associative memory test circuit under development will be discussed and the overall theme that a GaAs associative memory may provide an important role In future highperformance systems will be presented. 1 .

Two types of acoustooptic compressing photodetector structures suitable for continuous wave or long pulsewidth signals are described. The first compressing photodetector structure utilizes the subthreshold operation of carrier transport over the blooming gate to generate a compressing transfer characteristic. The second compressing structure utilizes the Coulombic repulsion of carriers at high carrier densities to generate a compressing transfer characteristics. The first structure is optimum for long integration times (10 to 200 microns), while the second structure is appropriate for short integration times (1 to 20 microns). Both detector structures initially exhibit an integration characteristic followed by a compresing characteristic. In both cases, the onset of the compressing characteristic is adjustable by varying the offset bias between the blooming gate and the imaging gate. The first detector structure exhibits a logarithmic compressing characteristic while the second detector structure exhibits a square-root compressing characteristic. Simulation models have been developed for both detector structures.

Ultra low profile (ULP) fiber optic transmitters and receivers have been developed which meet the 0.120 inch height requirement of military avionic applications. Field usable fiber optic connectors have been developed which provide highly efficient fiber coupling from -55 to +125 C. These devices are fabricated using soldering and laser welding techniques to produce packages which contain no organic materials. Both 1300 and 850 nm devices have been built which operate at 1.3 gigabits per second.