Mr. TeHung Wu Profile

TeHung Wu

Senior Manager at Siemens EDA

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Publications (7)

Proceedings Article | 14 October 2011 Paper

SMO applied to contact layers at the 32nm node and below with consideration of MEEF and MRC

Te-Hung Wu, Robert Sinn, Bob Gleason, JongDoo Kim, Jiyoung Hong, Sejin Park, Sukjoo Lee

Proceedings Volume 8166, 81660V (2011) https://doi.org/10.1117/12.896503

KEYWORDS: Photomasks, Source mask optimization, Fiber optic illuminators, SRAF, Logic, Optimization (mathematics), Critical dimension metrology, Semiconducting wafers, Detection and tracking algorithms, Image segmentation

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Proceedings Article | 26 March 2007 Paper

SEM based data extraction for model calibration

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, George Bailey, Te Hung Wu, Chia Wei Huang, Sheng Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6520, 65203B (2007) https://doi.org/10.1117/12.707353

KEYWORDS: Data modeling, Scanning electron microscopy, Calibration, Process modeling, Image processing, Optical proximity correction, Semiconducting wafers, Metrology, Resolution enhancement technologies, Feature extraction

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The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

Proceedings Article | 21 March 2007 Paper

A systematic approach for capturing interconnects hot spots

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, Te Hung Wu, Chia Wei Huang, Shen Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6521, 65211C (2007) https://doi.org/10.1117/12.713521

KEYWORDS: Semiconducting wafers, Photomasks, Image processing, Overlay metrology, Integrated circuits, Lithography, Resistance, Classification systems, Integrated circuit design, Transistors

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Proceedings Article | 15 March 2006 Paper

Improvement of OPC accuracy for 65nm node contact using KIF

Te Hung Wu, C. L. Lin, Ming Jui Chen, Zen Hsiang Tsai, Chen Yu Ao, H. C. Thuang, Jian Shin Liou, Chuen Huei Yang, Ling Chieh Lin

Proceedings Volume 6155, 61550M (2006) https://doi.org/10.1117/12.657900

KEYWORDS: Optical proximity correction, Data modeling, Scanners, Lithography, Photomasks, Projection systems, Optical calibration, Calibration, Lithographic illumination, Critical dimension metrology

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Proceedings Article | 12 May 2005 Paper

Novel illumination apertures for resolution-enhanced technology and through-pitch critical dimension control

I. Huang, Ling Lin, Chin Lin

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.599559

KEYWORDS: Photomasks, Optical proximity correction, Fiber optic illuminators, Resolution enhancement technologies, SRAF, Semiconducting wafers, Cadmium, Lithography, Critical dimension metrology, Manufacturing

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Proceedings Article | 12 May 2005 Paper

Feasibility study of sub-65nm contact/hole patterning

Yung Cheng, Te Wu, C. Lin, Sheng Chang, Benjamin Lin

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.599571

KEYWORDS: Lithographic illumination, Optical lithography, Lithography, Logic, Optical proximity correction, Photomasks, Resolution enhancement technologies, Printing, Manufacturing, SRAF

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Proceedings Article | 4 May 2005 Paper

Advanced microlithography process with multiple-chemical trim technology

Te Hung Wu, Ling Chieh Lin, C. L. Lin

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.598447

KEYWORDS: Line width roughness, Chemical reactions, Photoresist processing, Line edge roughness, Critical dimension metrology, Image processing, Resolution enhancement technologies, Semiconducting wafers, Optical lithography, Coating

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Showing 5 of 7 publications

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