This paper presents a new digital watermarking method, which majors improvement method realised based on single-chip FPGA. The procedure includes dividing the input digital image by block, block selection, sorting the pixel values within the blocks. The data is embedded by using new difference and new histogram-modification-strategy. The definition of new difference takes the position of maximum and the second large value pixel into account. Which is help for to the blocks, in which maximum value equal to the second largest. This algorithm can use these pixel blocks to embed data in. The key algorithm is based on the FPGA, using Verilog HDL language and graphical input method to design on the Quartus II 13.0 software platform. And the processed pixel value will be passed to the computer, providing experimental data for analysis and comparative.
Hydrological monitoring is recognized as one of the most important factors in hydrology. Particularly, investigation of the tempo-spatial variation patterns of water-level and their effect on hydrological research has attracted more and more attention in recent. Because of the limitations in both human costs and existing water-level monitoring devices, however, it is very hard for researchers to collect real-time water-level data from large-scale geographical areas. This paper designs and implements a real-time water-level data monitoring system (MCH) based on ZigBee networking, which explicitly serves as an effective and efficient scientific instrument for domain experts to facilitate the measurement of large-scale and real-time water-level data monitoring. We implement a proof-of-concept prototype of the MCH, which can monitor water-level automatically, real-timely and accurately with low cost and low power consumption. The preliminary laboratory results and analyses demonstrate the feasibility and the efficacy of the MCH.
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