Ms. Usha Rani Nelakuditi Profile

Usha Rani Nelakuditi

at VFSTR (Deemed to be Univ.)

SPIE Involvement:

Author

Publications (1)

This will count as one of your downloads.

You will have access to both the presentation and article (if available).

DOWNLOAD NOW

This content is available for download via your institution's subscription. To access this item, please sign in to your personal account.

Email or Username Forgot your username?

Password Forgot your password?

Show

Keep me signed in

No SPIE account? Create an account

Proceedings Article | 28 January 2013 Paper

Novel on chip-interconnection structures for giga-scale integration VLSI ICS

Usha Nelakuditi, S. Reddy

Proceedings Volume 8760, 876025 (2013) https://doi.org/10.1117/12.2012451

KEYWORDS: Transistors, Very large scale integration, Clocks, Multiplexing, Electronic design automation, Multiplexers, Visualization, Semiconductors, Design for manufacturability, Manufacturing

Read Abstract +

Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

My Library

You currently do not have any folders to save your paper to! Create a new folder below.

Folder Name

Folder Description

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks. You are receiving this notice because your organization may not have SPIE eBooks access.*

*Shibboleth/Open Athens users─please sign in to access your institution's subscriptions.

To obtain this item, you may purchase the complete book in print or electronic format on SPIE.org.

ORGANIZATIONAL
Sign in with credentials provided by your organization.

Organizational Username

Organizational Password

Show/Hide Password

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members:

Non-members: ADD TO CART

Keywords/Phrases

Search In:

Publication Years