Integrated Circuit (IC) fabrication requires performing a long sequence of complex process steps. Among them, photolithography patterning plays the most important role to define the dimensions, doping regions, and intercon nections for each device. With the advancement of lithographic processing, minimum feature sizes continue to shrink, and the devices become denser. At the same time, the specifications for overlay accuracy, wafer critical dimension uniformity, and acceptable focus deviations also become tighter. Hence, even nanometer-sized defects on wafer substrates can ha ve a crucial impact on the quality of the lithographic exposures and limit the performance of such devices. Detection and elimination of such surface defects (“focus spots”) at the early stage of processing have been of primary concern to prevent the loss in manufacturing productivity and significant product yield degradation. In this paper, we present a focus spot monitoring framework to detect focus spots and chuck spots accurately by using wafer leveling data. We discuss different strategies how to detect focus spots, how to classify them, and how to monitor and correct them effectively. We evaluate existing focus spot monitoring solutions and how to improve upon them. Altogether, a stable, reliable focus spot monitoring solution is described for optimal focus corrections and rework decisions.
Process window qualification using focus-exposure wafers is an essential step in lithography and a key use case for CD-SEM metrology. An automated analysis using the correlation between CD and focus/dose is easily possible but rarely done due to missing safety checks. Pattern fidelity that is analyzed by eye and problematic focus/dose conditions that may cause pattern degradation are excluded by hand. Specifically, when EUV lithography is utilized for exposing the most critical layers, roughness estimation becomes much more important, as it will restrict the process window further. We develop and describe unbiased and stable roughness estimates for contact hole patterns and integrate them into the process window analysis pipeline and inline monitoring routine. The analysis goes beyond simple roughness values and can detect a variety of possible CD-SEM measurement problems and shape deviations as well. Furthermore, we introduce a novel image-based machine-learning approach to detect outliers and quantify defective or abnormal patterns. Notably, the underlying model does not require knowledge of the types of CD features or design information for which outliers should be detected. We demonstrate that the approach can reliably detect local defects and a variety of other pattern anomalies. Using the generated visualizations, images with anomalous features can be flagged automatically and the locations of the defects or deviations are pinpointed. The approach yields not only the final missing piece in automated process window qualification, but also new opportunities to monitor pattern fidelity in lithographical semi-conductor processes.
Overlay is one of the critical parameters and directly impacts yield. Due to high metrology cost, only a small number of wafers are measured per lot. To this end, virtual metrology (VM) aims to provide valuable information about the nonmeasured wafers with little to no additional cost. VM leverages historical per-wafer measurements from exposure tools and processing equipment collected at previous process steps to report overlay on every wafer. As data-driven approaches gain more adoption in the semiconductor manufacturing, machine learning (ML) is a natural choice to tackle this task. In this paper, we present the strategies of learning overlay prediction models from exposure and process context data as well as the steps for achieving desired prediction performance, including data preparation, feature selection, best modeling methods, hyperparameters tuning and objective. We demonstrate our methodology on a large HVM dataset under stable APC conditions.
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