Nanoimprint lithography (NIL) is a promising technology on next generation lithography for the fabrication of semiconductor devices. NIL is a one-to-one lithographic technology with a contact transfer methodology using templates. Therefore, critical dimension (CD) error and defect performance of templates has direct impact on wafer performance. The previous paper reported that the self-aligned double patterning (SADP) process on master template had better performance on resolution and defect performance [2]. In proceeding with development of SADP template process technology, we found that CD errors occurred in the area with a pattern density change. CD control over any pattern density is one of the critical issues. In this report, we have investigated the impact of the proximity effect correction (PEC) and fogging effect correction (FEC) parameters for electron beam writing on gap space and core space. It was found that the optimal PEC parameter for resist CD is not the best for the core space and the gap space. The resist CD is uniform, but there is a difference in resist shape on the local pattern density variation. It was also found that the core space had dependency on global pattern density even if the optimal FEC parameter for resist CD was applied. FEC can correct resist CD, but it cannot adjust resist shape. By using the optimal PEC and FEC parameters for SADP process, the gap space range of 0.6 nm and the core space range of 0.5 nm were successfully obtained.
An essential element of sub-15 nm nanoimprint lithography is to create fine patterns on a template. However, it is challenging to create sub-15 nm half-pitch patterns on a template by direct drawing with a resist, owing to poor resolution and low sensitivity. We are currently researching the development of sub-15 nm half-pitch patterns by applying self-aligned double patterning on a template. The defect density of the template has not yet reached a high-volume manufacturing level. The aim of our study is to achieve a defect density of less than 1 pcs/cm2 for sub-15 nm templates. To achieve this, we need to overcome stochastics-induced resist defects. We aim to determine the mechanism of defect formation by observing the details of the defects. We challenged resist-pattern inspections using a grazing-incidence coherent scatterometry microscope, which illuminated an extreme ultraviolet light to the resist pattern and detected the diffraction signal from the pattern. This study was conducted in collaboration with University of Hyogo and Kioxia Corporation. In this paper, we present the results of damage evaluations and resist-pattern inspections.
Nanoimprint lithography (NIL) is promising technology for next generation lithography for the fabrication of semiconductor devices. The advantages of NIL are simpler process, less design rule restriction, which lead to lower cost-of-ownership, compared with conventional optical lithography. NIL is one to one lithography and contact transfer technique using template. Therefore template quality variations impact on wafer performance directly. To introduce NIL technology to high volume manufacturing (HVM) of semiconductor devices, improvement of template quality is very important. In the situation of pattern size shrinking, it is necessary to improve CD uniformity and defectivity to achieve the target of HVM. So that high accuracy QA (Quality Assurance) tools are required to qualify CD uniformity and defectivity which are key metrics on high-end template development. In this paper, we show the current status of template development for sub15nm NIL. For the template fabrication, double patterning technologies were applied to extend pattern resolution limit. Template replication was also implemented by template replication system Canon FPA1100-NR2. Finally we will show QA examples for high accuracy template by using key metrics such as CD uniformity, defectivity and Cross-sectional profile.
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