The InAs/InAsSb nBn structure detector without Ga (GA-free) has fewer internal defects, and the barrier blocks majority carrier while allowing the normal transport of photogenerated carriers. The unique structure can effectively suppress the generation-composite current generated by SRH, and achieve low dark current at high operating temperature. In this paper, a mid-infrared Ga-free nBn T2SL detector is investigated. The device exhibited 7.43x10-6 A/cm2 under 0.5 V bias at 127 K. At 120K, the detector achieves quantum efficiency values of 56%, exhibits excellent photoelectric performance.
The interfacial asymmetry and compositional disorder caused by atomic segregation and exchange significantly affect the electrical properties of the InAs/InAsSb superlattice, leading to deviations from original designs. The study presents a quantitative analysis of the compositional asymmetry of the superlattice and its effects using a segregation model and 8-band k.p model. The composition disorder at each interface, primarily induced by Sb segregation, is examined through the reconstruction of the actual atomic sequence structure based on scanning tunneling microscopy results. Three different atomistic structures of the superlattice are modeled using the k.p method, including the ideal MBE-growth structure, a rebuilt structure with Sb segregation only at the InAs-on-InAsSb interface, and a rebuilt structure with Sb segregation at both interfaces. The results of the modeling highlight the significant influence of Sb segregation on the electronic properties of InAs/InAsSb superlattices.
This paper first introduces the application background of detection and processing integrated intelligent image sensor, and proposes an overall architecture of intelligent image sensor that uses hybrid stacking process for vertical interconnection. Among them, the top pixel layer mainly contains 10K×10K 5um pixel array and row and column drive array, which gives the pixel structure, simulates and analyzes the pixel noise index and effectively guides the design of the readout circuit structure. The lower chip layer mainly contains readout circuits, image signal processing ISPs, general-purpose CPU units, AI neural processing units, and on-chip SRAM. The image signal processing ISP function and the AI neural processing unit are introduced in detail, and the FPGA verification results of the AI neural processing unit are given.
This paper first introduces the application background of detection and processing integrated intelligent image sensor and proposes an overall architecture of intelligent image sensor that uses hybrid stacking process for vertical interconnection. Among them, the top pixel layer mainly contains 10K×10K 5 um pixel array and row and column drive array, which gives the pixel structure, simulates and analyzes the pixel noise index and effectively guides the design of the readout circuit structure. The lower chip layer mainly contains readout circuits, image signal processing ISPs, general-purpose CPU units, AI neural processing units, and on-chip SRAM. The image signal processing ISP function and the AI neural processing unit are introduced in detail, and the FPGA verification results of the AI neural processing unit are given.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.