A method to fabricate a very thin channel body Fin-FET and Tri-gate MOSFET is presented. 8% Attenuated Phase-shift mask (APSM) and single phase chrome-less mask (CLM) techniques are evaluated to pattern fins in sub-50 nm regime using KrF lithography scanner with a maximum numerical aperture of 0.68. Some of the issues of single phase CLM technique with respect to fin patterning are highlighted. Dual Exposure With Shift (DEWS)’ is introduced to pattern gate lines down to 80 nm using binary mask.
Scattering bars have been an essential component of the reticle layout design to increase process yields for devices with design rules that are 0.18 um and below. These are sub-resolution features and make semi isolated and isolated features to be imaged like dense features as the illumination conditions are always decided by most dense pitch. With the use of scattering bars the depth of focus and iso-dense matching get improved. This results in better critical dimension (CD) control in the wafer fabs. Scattering bar has been helpful in extending the limit of optical lithography. This paper describes the effect of scattering bars width and separation on the printed feature size. Trench patterning is studied at different partial coherence and lens numerical aperture (NA). Also, the effects are compared for binary and 8% attenuated phase shift mask (APSM). The patterned feature size is found to be more sensitive to scattering bar parameters at small NA and low partial coherence. The CD of the feature has strong dependence on scattering bar separation than size and also influenced by the NA and sigma. An interesting phenomenon at low partial coherence is the presence of deep valley or 'V' shaped CD trend in scattering bar separation versus CD curve. CD dip is more on APSM as compare to binary mask.
A CMOS compatible single resist layer lift-off process for forming patterns on a substrate is described. Unlike in most other methods, an ion bombardment is employed here to harden the top of the resist leaving the sidewall of the resist unaffected. The resist is then treated to a low temperature O2 plasma etching process to achieve a T-shaped undercut profile. This process is found to be simple, repeatable and controllable. Resist profile with adjustable overhang length and the sidewalls of the resist profile with an almost T-shape could be achieved with the help of the process described in the current work. Such increased overhang length prevents metallization of the sidewalls of the resist, and thus facilitates more rapid removal of the resist during lift-off. The process starts from a patterned resist layer having vertical resist profile. It is then subjected to Ion bombardment to harden the top surface of the resist leaving the sidewalls unaffected. The ions are directed at sufficient dose and energy to cause the top of the resist mask to get hardened. Subsequently, the resist patterns are subjected to a low temperature isotropic plasma etching process resulting in an under-cut T-shaped resist profile. This process is highly suitable for MEMS application where metals like Cr, Au, Cu etc are frequently used but are difficult to dry etch.
The current work was done jointly between Institute of Microelectronics, Singapore and Tokuyama Corporation, Japan. Here the patterning performance of four different developers was evaluated. Three of these were with surfactant and one was without surfactant. The parameters evaluated were resist thickness loss, resist contrast, process windows such as depth of focus and exposure latitudes, across wafer critical dimension (CD) uniformity, and post pattern defect density. Feature sizes of 180 nm and 150 nm were evaluated for litho process latitudes. CD uniformity was also evaluated for 180 nm and 150 nm geometries. The resist loss was found to be minimum for developer A which was without surfactant. The depth of focus and exposure latitude of smaller geometry (150nm lines) in general showed better values for developers with surfactants. Developer solutions with surfactant also gave better across wafer CD uniformity for smaller geometries (150nm). Post pattern defects were found to be least with developer C that which contained nonionic type of surfactant and cationic one. Defects were highest for developer B which contained nonionic type of surfactant. The addition of optimum surfactant to developer has potential for reducing defects to lower levels and achieves better across wafer CD uniformity for smaller geometries.
Intra-field lens aberrations and distortions affect the shape of contact hole patterning. This effect is more severe with defocus. In this paper, we have studied the effect of difference in horizontal and vertical diameter of a contact hole on the lithography process window for different illumination conditions using a 0.68NA step and scan system. It is found that the depth of focus (DOF) for 0.22um contact hole patterning shrinks considerably taking into account the horizontal and vertical diameter measurements as compared to the average diameter measurements alone.
BARC (Bottom Anti-Reflective Coating) is used to minimize thin film interference effects such as swing curve, standing waves and resist notching in the photolithography process. In the 'via first' dual damascene approach, BARC also acts as a protecting layer for the substrate underneath the via during the trench etch step. Conformal BARC is normally used for the patterning due to its uniform film thickness over the surface topography, which can provide good CD control. However, conformal BARC may not be able to provide sufficient substrate protection at the via bottom as BARC film remaining in the via may not be thick enough. In comparison, planarizing BARC has better via filling property which can provide sufficient protection for the via bottom substrate. In this study, four different BARCs; conformal and planarizing at two different viscosities, were evaluated for the 'via first' dual damascene copper patterning process. Low viscosity BARC was used to obtain a thin BARC coating for the partial via filling, while high viscosity BARC was used for full via filling process. We evaluated the performance of BARCs for via filling, depth of focus, exposure latitude, iso-dense feature bias and CD control. Dual damascene pattern was etched using two different etch recipes and we compared the performance of all the four BARCs for final etched pattern formation.
In this work, different overlay targets were evaluated for the Via first process with conventional USG dielectric. The etch stop layer nitride thickness was limited at 500 A as increasing this thickness will increase the RC delay which is undesirable. A series of targets were evaluated to find out the best performer. Target evaluation was done by their appearance, static repeatability, dynamic repeatability, target correlation, Tool induced shift, Overall misregistration, and residuals. Lot comparisons have also been done using selected targets. Lot average misregistrations (with the best target-2micrometers trench) of 9nm (X + 3(sigma) ), and 15nm (Y + 3(sigma) ) were obtained for the Metal 2 (M2) aligning to Via 1 (V1) level. The different Bar in Bar target structures evaluated were: a. Trench in trench : 1 micrometers and 2 micrometers trenches. b. Wall in wall : 1 micrometers Bars and 2 micrometers Bars. The trench in trench structures were found to work better than bar in bar for conventional dielectric Via first approach. The 2micrometers thick trenches gave the best results for target correlation, dynamic repeatability, and residual values. Metal 1 to metal 2 targets also gave good results and could be used. For low K dielectric and copper integration, a dual hard mask scheme was used. The dual hardmask was used to minimize the interaction of organic dielectric with organic barc and deep UV resist layer as this sometimes gives rise to poisoning issues. For the Organic Low K dielectric and Copper, where the dual hard Mask scheme was followed, the Wall in Wall target gave good contrast and the best results.
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