This paper proposes a new methodology that can greatly accelerate Manufacturability Analysis & Scoring (MAS) deck runtime. The intention of this work is to provide a quick preview check to ensure that a new design will pass MAS signoff. Instead of running the deck on the full design, the input design is sampled down to a few random locations which are then analyzed. Furthermore, the actual MAS checks are replaced by an ML trained lookup methodology that keys off very simple design parameter like layer area density and layer perimeter density. The output of the deck is a simple PASS/FAIL statement and a range forecast for the MAS score based on a statistical assessment. We can demonstrate 4x runtime improvement while incurring minor tradeoffs for accuracy.
KEYWORDS: Data modeling, Machine learning, Neural networks, Design and modelling, Design for manufacturing, Principal component analysis, Correlation coefficients, Singular value decomposition, Mathematical optimization, Lithography
Design for Manufacturability (DFM) physical verification checks using supervised Machine Learning (ML) are developed and optimized to identify via-metal enclosure weak points to prevent via opens caused by line-end shortening post-retargeting. Various methods for generating feature vectors and neural network architectures are evaluated for optimizing training time and ML model quality. Techniques include applying PCA to image-based density vectors generated from layout clips to identify the principle components or using localized layout features directly for model training. Results show that for a sample size of 300k vias, the image-based density vectors versus localized layout feature vectors achieve similar correlation coefficients of 0.95 and normalized RMSE of 0.11, with a training time of 10+ hours versus 1+ minute, respectively.
Retargeting-aware Design for Manufacturability (DFM) via-metal enclosure checks are developed using supervised machine learning to identify critical weak points to aid layout fixing. The machine learning model is developed using a neutral network architecture. Seventeen localized layout features were extracted, including: side and line end via-metal enclosure, via spacing to the neighboring features, and metal coloring. The extracted features were used to form feature vectors to train and generate a machine learning-based model for predicting post-retargeting, via-metal enclosures. This method was demonstrated on 22nm layouts. Using a neural network with 2-hidden layers, the predicted via-metal enclosure versus the actual data correlate with an R2 of 0.91 and an RMSE 0.0067.
This work is evaluating Machine Learning (ML) architecture options for weak point detection methods embedded in Design for Manufacturing (DFM) signoff tools. As Deep Learning based models have been released into the customer design enablement space, we are investigating the tradeoffs between model simplicity, run time and prediction accuracy. With simpler model architectures, additional options for data augmentation become available that can potentially result in better model accuracy. For example, noise introduction in the training data set can help prevent overfitting and thus results in better model accuracy.
With more advanced semiconductor technologies, identifying process weak points becomes more complex as multiple layers need to be taken into consideration. In recent years, traditional rule based weak point identification has been augmented by pattern matching to pinpoint and fix possible design weak points. Traditional methods of pattern definition are done by profiling the designs for weak points to capture the patterns of interest for applying opportunistic fixes. Patterns are usually handcrafted by taking process information into account, and applying fixes on the design features. Some fail modes have emerged recently that are a result of very complex multi layer interactions. These types of weak points are very difficult to define comprehensively with traditional pattern matching.
Recently, deep learning has undergone a rapid development and tools are now available that can learn based on large amounts of process data. We have harnessed this to address the problem of identifying complex weak points with low escape rates. In this paper, we provide a review on a deep learning based weak point detection flow taking retargeting/opc/orc simulations into account as training data. Using the deep learning approach, the process data is abstracted as an encrypted machine learning model, and released to designers as part of the GLOBALFOUNDRIES (GF) DRC+ tool. This tool is shipped with the PDK, and can be used to fix the design, mitigating process weak points.
This paper begins with a brief introduction to the deep learning TensorFlow model using Convolutional Neural Network (CNN) widely used for image detection. Then we focus on feature density vector (DSV) generation to extract the layout parameters and labels used for training the model. Experimental analysis is also provided to compare recall and precision metrics of POR and ML methods in detecting the weak point on a via layer at process window conditions. Our case study shows that the ML flow improves the pattern capture rate by 34% over standard hotspot detection methods. As a conclusion, we will also brief on our future work leveraging the ML flow for other weak point detections.
Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle, in turn saving time and efforts. In this paper, we describe a new bottom-up approach to layout risk assessment that can rapidly identify unique patterns in layouts, and in combination with techniques like feature filters, location mapping and clustering, can pre-determine their criticality. A massive highly performant pattern database of single and multilayer patterns, along with their features and locations, forms the core of the system. While pattern analyses may be pertaining to the short range of design space, silicon defects and simulations extend to a much larger scope. Therefore, the database is extended to defect data extracted from Silicon inspection tools like Bright Field Inspection (BFI) and Scanning Electron Microscopy (SEM). When stored in an optimized manner, it can aid fast and efficient large data analysis and machine learning within critical tapeout review time which is typically a few days. Machine learning combined with design feature filters can then be used for anomaly detection and failure prediction at layout, layer and pattern levels. As a result, outlier patterns can be visually reviewed and flagged for custom targeted simulations and silicon inspection. Further, adding new layout patterns to the pattern database will make it possible to repeat this exercise for subsequent new layouts.
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