Proceedings Article | 18 March 2019
Subhadeep Kal, Yusuke Oniki, Matthew Falugh, Cheryl Pereira, Qi Wang, Frank Holsteyns, Jeffrey Smith, Aelan Mosden, Kaushik Kumar, Juergen Boemmels, Julien Ryckaert, Peter Biolsi, Trace Hurd
KEYWORDS: Etching, Field effect transistors, Group IV semiconductors, Isotropic etching, Silicon, Gallium arsenide, Nanowires, Semiconductors, Transistors, Standards development
Area scaling without compromising on performance has become a challenge for technology nodes beyond N7. Gate all-around (GAA) device architecture for N5 and beyond technology nodes is emerging as a promising solution and is being heavily investigated by the semiconductor industry. Imec has recently demonstrated that GAA transistor design offers 50% area scaling for both standard cells and SRAM memory cells, by stacking NMOS and PMOS wires on top of each other (also called complimentary FET (CFET)). In addition, design technology co-optimization analysis indicates that CFET architectures meet the N3 power and performance requirements (Ryckaert et.al.; SPIE 2018, VLSI technology symposium 2018). However, integration and fabrication of such CFET architectures become significantly challenging. A primary requirement for GAA (CFET or separate NMOS/PMOS) devices is the formation of silicon channels / nanowires (NW)/nanosheets (NS). For CFET fabrication, a quintessential challenge is an etching method which can provide required selectivity to recess an epitaxially grown material selective to either NMOS or PMOS channel materials into a low-k gate spacer with adequate etch selectivity in an isotropic manner such that stacked wires or sheets can be formed either sequentially or simultaneously.
In the article, we will focus mainly on the Si NW/NS formation (or SiGe etch). Fabricating such NW/NS architecture requires two extremely selective, isotropic, and precise SiGe etches. As shown in Fig.1, step 2 (“SiGe cavity etch”) & step 8 (“channel release”). After the “SiGe cavity etch”, an ALD film of low-k spacer is deposited as the inner spacer (Fig.1, step 3). The SiGe cavity etch (Fig.1, step2) must be controlled with an extreme accuracy and have a straight etch front. The cavity etch will effectively define the inner spacer thickness in the area above and below the Si NW, after the inner spacer etch (step 4, Fig.1). A precise SiGe etch control is essential for the cavity formation, because: (1) if the SiGe recess is below target, the reformed inner spacer thickness will be under specification and may result in high parasitic capacitance between gate and source/drain expected. (2) If the SiGe recess is above target, the reformed inner spacer will penetrate into the replacement gate and will decrease the amount of gate metal wrapping around the nanowire and may impact channel length (Lg). Furthermore, in addition to the above requirements, etch selectivity towards the dummy gate, hard mask, oxide (STI, ILD0), and low K material around the gate (as shown in Fig 1) is essential. We will also demonstrate the process performance for “channel release” as mentioned earlier (Fig 1, step 8) and inner spacer etch (Fig 1, step 4) .To address the requirements described above, a process flow enabled with extremely high selective etches, where the selectivity is a function of film properties and/or etch chemistry is a quintessential advantage. In this article, we will demonstrate the significance of such selective etches for Si NW/NS fabrication.
