As feature sizes diminish and correction flow complexity increases, it becomes extremely difficult to create homogeneous mask synthesis correction recipes that can pass lithographic verification without some failing hotspots. When encountered in the production line, these areas are frequently fixed quickly so the tapeout can resume and time-tomask is preserved as much as possible. However, these hotspots may occur in future designs, so it is beneficial to update the standard correction recipe with this hotspot information and avoid verification failures before they occur. This paper examines inserting unique hotspot corrections into the standard correction flow using pattern matching to identify the hotspot areas. Standard correction recipes can be updated to accept these hotspot areas and adjust recipe parameters or correction techniques in a standard manner so that these hotspots will be fixed automatically. This automation technique minimizes human interaction with the recipe.
Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern [1]. When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.
We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
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