In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.
In modern digital integrated-circuit designs, standard-cell libraries are key foundations. The increased leakage current, complicated design rules, and restrictive layout space make the task of designing standard cells meeting both electrical characteristic requirements and layout constraints a significant challenge. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. In this work, as a refinement of the existing approaches, a new method is proposed to find suitable initial values and reduce the electric characteristics deviation. Preliminary results indicate that the proposed method can be effective in 20-nm-grade standard-cell optimization.
In subwavelength lithography, printed patterns on the silicon wafer suffer from geometric distortions and differ from the original design. These nonrectangular patterns can seriously affect electrical characteristics and circuit performances. We extend the verification of location-dependent weighting method and further propose three single equivalent gate length (EGL) extraction methods for representing each nonrectangular gate (NRG) transistor with a single EGL model. These methods are applied to sub-20-nm fully depleted silicon on insulator (FDSOI) circuits to predict the postlithography performances. An in-house extreme ultraviolet lithography simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct three-dimensional nonrectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods is verified with TCAD circuit simulations. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the EGLs extracted from off-state only data, and from data lumping both off- and on-states, respectively, can each predict SRAM electrical characteristics with overall error <1 % , or a factor of 5 accuracy improvement over the EGLs extracted without the weightings. These methods could be used to simulate large-scale sub-20-nm FDSOI circuits with NRG transistors caused by nonideal optical effects.
The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, has been confronted with difficulties in advanced nodes. For developing new metrology solutions, high-quality test structures fabricated at specific sizes are needed. Electron-beam direct-write lithography has been utilized to manufacture such samples. However, it can encounter significant-resolution difficulties and may require complicated process optimization in sub-10-nm nodes. Therefore, we investigate the feasibility and patterning control of metrology test structures fabricated by helium ion beam (HIB) direct milling and HIB direct-write lithography, where HIB has the sub-nm resolution in nature. Results show that features down to 5 nm are resolvable without any resolution enhancement technique by HIB direct milling. For HIB direct-write lithography, features down to International Roadmap for Devices and Systems 1.5-nm node are also resolvable without optimization from the lithography simulation. Furthermore, patterns beyond the 1.5-nm node can be achievable with the help of the proximity effect correction technique. Preliminary results demonstrate that HIB direct milling and HIB direct-write lithography can be a promising alternative for fabricating pit-type programmed defects (PDs) and bump-type PDs, respectively. In conclusion, HIB is suggested to be a potential tool to fabricated test structures for developing advanced metrology solutions in sub-7-nm nodes.
The availability of metrology solutions, one of the critical factors to drive leading-edge semiconductor devices and processes, can be confronted with difficulties in the advanced nodes. For developing new metrology solutions, highquality test structures fabricated at specific sizes are needed. Electron-beam direct-write lithography has been utilized to manufacture such samples. However, it can encounter significant-resolution difficulties and require complicated process optimization in sub-10-nm nodes. This study investigates the feasibility and patterning control of metrology test structure fabrication by helium-ion-beam direct-write lithography (HIBDWL). Features down to IRDS 1.5-nm node are resolvable without needing any resolution enhancement technique from the lithography simulation. Further, patterns beyond 1.5-nm node can be achievable with the help of proximity effect correction technique. Preliminary results of simulation demonstrate that HIBDWL can be a promising alternative for fabricating programmed defects (PDs) and test structure to develop advanced metrology solutions in sub-7-nm nodes.
Model-based optical proximity correction (MPOPC) has been well adopted in subwavelength lithography for integrated-circuit manufacturing. Typical MBOPC algorithms involve with iteratively moving the layout polygon edges to reduce the edge placement errors (EPEs) predicted by the lithography model. At each iteration, the amounts of movement are mainly determined by the values of the EPEs and the correction factors (CFs). Since full-chip lithography simulation is very computation intensive, it is highly desirable to minimize the number of iterations for acceptable run times, by selecting suitable CFs. In practical applications, the CFs are usually heuristically determined and applied globally throughout the correction regions. This approach efficiently reduces the EPEs at most of the target points but the entire convergence can be hampered at a relatively small number of hot-spot locations. This work investigates the effectiveness of improving the overall convergence by introducing both global and local CFs, and approaches to utilize machine-learning techniques to estimate the hot-spot locations and associated local CF values.
In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns can affect electrical characteristics and circuit performances seriously. In this work, we extend the verification of location-dependent weighting method and further propose three single conventional equivalent gate length (EGL) extraction methods for representing each non-rectangular gate transistor with a single EGL model. These methods are applied to sub-20nm FDSOI circuits to predict the postlithography performances. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods are verified with TCAD circuit simulations. A 2D EGL circuit simulation method in TCAD is proposed instead of 3D EGL method to reduce the simulation time required. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the off-state EGL (EGLoff) with weightings is good enough. These methods could be used to simulate the non-rectangular transistors applied to sub-20nm FDSOI circuits including 6T-SRAM caused by non-ideal optical effects in industrial processes.
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