Mr. Ji-Suk Hong Profile

Ji-Suk Hong

Principal Engineer at SAMSUNG Electronics Co Ltd

SPIE Involvement:

Author

Area of Expertise:

Lithographic DFM , Statistical variability modeling , OPC , Memory cell fail rate modeling

Publications (13)

Proceedings Article | 1 May 2023 Presentation + Paper

A novel approach to etch-process-aware intensive layout retarget

Jeeyong Lee, Yangwoo Heo, Ryanggeun Lee, Sangwook Kim, Jisuk Hong, Kyoil Koo, Changmook Yim, Jungmin Kim, Sooyong Lee, Joonsung Kim, Dongho Kim, Seung-Hune Yang, Seongtae Jeong

Proceedings Volume 12499, 124990C (2023) https://doi.org/10.1117/12.2657880

KEYWORDS: Artificial intelligence, Feature extraction, Reflection, Optical proximity correction, Statistical modeling, Design and modelling, Machine learning, Modeling, Data modeling, Etching

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Proceedings Article | 20 March 2019 Presentation + Paper

Automatic correction of lithography hotspots with a deep generative model

Woojoo Sim, Kibok Lee, Dingdong Yang, Jaeseung Jeong, Ji-Suk Hong, Sooryong Lee, Honglak Lee

Proceedings Volume 10961, 1096105 (2019) https://doi.org/10.1117/12.2514884

KEYWORDS: Computational lithography, Image processing, Binary data, Image classification, Process modeling, Data modeling, Neural networks, Photomasks, Lithography

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Proceedings Article | 20 March 2018 Presentation + Paper

Thread scheduling for GPU-based OPC simulation on multi-thread

Heejun Lee, Sangwook Kim, Jisuk Hong, Sooryong Lee, Hwansoo Han

Proceedings Volume 10587, 105870P (2018) https://doi.org/10.1117/12.2295696

KEYWORDS: Graphics processing units, Communication engineering, Electronics, Tolerancing, Optical lithography, Semiconductors, Computer simulations, Optical proximity correction

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Proceedings Article | 13 March 2009 Paper

Score-based fixing guidance generation with accurate hot-spot detection method

Yong-Hee Park, Dong-Hyun Kim, Jung-Hoe Choi, Ji-Suk Hong, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo, Jun-Dong Cho

Proceedings Volume 7275, 72750P (2009) https://doi.org/10.1117/12.811840

KEYWORDS: Optical proximity correction, Lithography, Semiconducting wafers, Calibration, Optical lithography, Nanoimprint lithography, Image quality, Photomasks, Semiconductors, Image enhancement

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Proceedings Article | 13 March 2009 Paper

Statistical approach to design DRAM bitcell considering overlay errors

Yu-Jin Pyo, Dae-Wook Kim, Jai-Kyun Park, Ji-Seong Doh, Hyun-Jae Kang, Ji-Suk Hong, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo

Proceedings Volume 7275, 72751L (2009) https://doi.org/10.1117/12.815341

KEYWORDS: Overlay metrology, Surface plasmons, Critical dimension metrology, Statistical analysis, Manufacturing, Resistance, Error analysis, Monte Carlo methods, Optical lithography, Process control

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Proceedings Article | 14 May 2007 Paper

DFM based on layout restriction and process window verification for sub-60-nm memory devices

Soo-Han Choi, Dai-Hyun Jung, Ji-Suk Hong, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6607, 66071A (2007) https://doi.org/10.1117/12.728958

KEYWORDS: Data modeling, Lithography, Critical dimension metrology, Process modeling, Design for manufacturing, Finite element methods, Photoresist processing, Photomasks, Optical proximity correction, Data processing

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The adoption of the model-based OPC and RET does not guarantee enough process margin any more in the low k1 lithography because potential patterning defects by layout-induced hot spots reduce common process window. The introduction of the litho-friendly layout has faced practical limitation by the designers' short knowledge of the lithography and its impact on the layout. In this paper, we develop a novel method based on restricted design rules (RDR) and process window verification (PWV) to get rid of the layout-related process hot spots during the physical layout design. Since RDR consists of simple design rules familiar to designers and PWV is implemented on layout editor environment, this proposed method is easy to apply in the current design flow. Since memory core layout is designed with typical and repeated patterns, the restriction of layout by design rule enforcement is effective to remove hot spots in the core area. We develop a systematic RDR extraction method by designing test patterns representing repeated memory core patterns by simple pattern matching technique. 1-dimensional (1D, simple line and space pattern) and 1.5-dimensional (1.5D, complicated line and space pattern) test patterns are analyzed to take into account the printability. The 2-dimension (2D) test patterns split by contact pad size are designed to consider the overlap margin between related layers. After removing the hot spots with RDR violations on unit cell by auto-fixer, PWV is applied to detect the random hot spots located on peripheral area. Analyzing CD difference between measurement and simulation according to variation of resist cutting plane and focus, the optical model having physical meaning is generated. The resist model, which uses focus exposure matrix (FEM) data within the process margin of memory cell, can represent the photo process variations accurately. Implementing the proposed method based on RDR and PWV, depth of focus (DOF) of sub-60nm memory device is improved by 50% compared with the result of original layout.

Proceedings Article | 20 March 2006 Paper

Efficient OPC model generation and verification for focus variation

Yong-Hee Park, Yong-Chan Ban, Duck-Hyung Hur, Dong-Hyun Kim, Ji-Suk Hong, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6154, 61543B (2006) https://doi.org/10.1117/12.656762

KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Lithography, Photomasks, Semiconducting wafers, Optical lithography, Instrument modeling, Critical dimension metrology, Algorithms

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Proceedings Article | 15 March 2006 Paper

OPC and verification accuracy enhancement using the 2D wafer image for the low-k1 memory devices

Yong-Chan Ban, Dong-Yoon Lee, Ji-Suk Hong, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6154, 61540J (2006) https://doi.org/10.1117/12.656280

KEYWORDS: Scanning electron microscopy, Optical proximity correction, Calibration, Data modeling, Semiconducting wafers, Critical dimension metrology, Image enhancement, Image processing, Instrument modeling, Lithography

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Proceedings Article | 15 March 2006 Paper

MEEF-based correction to achieve OPC convergence of low-k1 lithography with strong OAI

Soo-Han Choi, A-Young Je, Ji-Suk Hong, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6154, 61540P (2006) https://doi.org/10.1117/12.656894

KEYWORDS: Optical proximity correction, Critical dimension metrology, Lithography, Lithographic illumination, Model-based design, Photomasks, Device simulation, Solid modeling, Immersion lithography, Nanoimprint lithography

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Proceedings Article | 12 May 2005 Paper

Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600249

KEYWORDS: Nanoimprint lithography, Photomasks, Optical proximity correction, Semiconducting wafers, Lithographic illumination, Lithography, Thin films, Scanners, Model-based design, SRAF

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Proceedings Article | 5 May 2005 Paper

New OPC methods to increase process margin for sub-70nm devices

Ji-Suk Hong, Dong-Hyun Kim, Sang-Wook Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600231

KEYWORDS: Optical proximity correction, Model-based design, Lithography, Optical lithography, Nanoimprint lithography, Process modeling, Data modeling, Semiconducting wafers, Scanning electron microscopy, Photomasks

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Proceedings Article | 28 May 2004 Paper

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

Ji-Suk Hong, Chul-Hong Park, Dong-Hyun Kim, Soo-Han Choi, Yong-Chan Ban, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535027

KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Critical dimension metrology, Instrument modeling, Etching, Process modeling, Lithography, Calibration, Error analysis

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Proceedings Article | 28 May 2004 Paper

Simulation-based critical-area extraction and litho-friendly layout design for low k1 lithography

Soo-Han Choi, Yong-Chan Ban, Ki-Heung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535008

KEYWORDS: Optical proximity correction, Lithography, Solid modeling, Photomasks, Image processing, Critical dimension metrology, Nanoimprint lithography, Semiconducting wafers, Electroluminescence, SRAF

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Showing 5 of 13 publications

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