In this paper we perform a foundational study on the impact of quartz etched depth, and optical density (OD) of mask opaque area, the 3D effect in ArF immersion lithography at advanced process node. The after development inspection (ADI) critical dimension (CD) variation may be caused by these 2 mentioned factors on the photomask, even the mask CD value of the measurement point is the same. Different cleaners and etchers which fix the same cleaning and etching time, induce different OD of reticle opaque patterns and several quartz etched depths. The relations between OD of reticle opaque patterns / quartz etched depth and ADI CD are the significant subject for successful pilot run which may moderate pilot run time and reduce rework costs in the lithography process. The focus of this study is the characterization of the correlation between OD of reticle opaque patterns / etched quartz depths and ADI CD. We experimentally study the structures from the theoretical introduction on the mask 3D phenomena, all of results are obtained using a MoSi binary ArF blank. A comprehensive wafer CD measurement result will be demonstrated in different OD of reticle opaque patterns and etched quartz depth, both simulation and experimentally based. The effect of fabricating the photomask quartz trenches will also be studied as well as the impact on through pitch CD and exposure latitude. The goal of this study is the demonstration of the practical influence on mask OD and the etched quartz depth of leading edge photomasks.
Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.
As technical advances continue, the pattern size of semiconductor circuit has been shrunk. Defect control becomes tighter due to decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained considerably shrunk circuit and ultra high density pattern for sub – 14 nm tech devices. Therefore particle source from all processes should be controlled extremely. Most of defects generated in mask fabrication processes have been mainly created during each unit process. In this paper, we introduce a study of airborne molecular contamination to Cr etching process. The impact of mask front-end handling system to defect generated in Cr etching process even in very lower concentration environment airborne molecular contamination. By the experiment results we will bring forward the possible defect generation mechanism. Based on this understanding, appropriate solution to mitigate defects caused by airborne molecular contamination to Cr etching process will be proposed.
Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design [1], [2]. This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.
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