Dr. Guillaume Chabanne Profile

Dr. Guillaume Chabanne

at Soitec

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Proceedings Article | 5 March 2022 Presentation + Paper

Cutting-edge silicon-on-insulator substrate technology for datacenter transceivers and sensing applications

Corrado Sciancalepore, Q. Wilmart, L. Ecarnot, D. Herisson, G. Chabanne, B. Szelag, A. Alami-Idrissi

Proceedings Volume 12005, 1200502 (2022) https://doi.org/10.1117/12.2605732

KEYWORDS: Silicon, Silicon photonics, Semiconducting wafers, Wafer-level optics, Transceivers, Optics manufacturing, CMOS technology, Photonics, Integrated optics, Waveguides

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Silicon-on-insulator (SOI) substrate technology has been the defining foundation of silicon photonics integrated circuits over the last 20+ years, fostering its commercial success in datacenter interconnects and promoting widespread adoption for high-speed optical transceiver products. More recently, novel applications could also leverage the silicon photonics toolset and ecosystem maturity to target newer, expanding markets, including consumer sensing for healthcare monitoring devices, LiDAR devices for the automotive, as well as optics-based advanced quantum computing and neural networks.

In such dynamic context, Photonics-SOI substrates design and the underlying Smart-Cut process need to relentlessly adapt in order to meet the evolving requirements of end-products and applications specifications, while addressing industrial high-volume manufacturability, high fabrication yields, cost-effectiveness, and related quality constraints. More specifically, the need for growing aggregated bandwidth density at low power dissipation in transceivers products as well as the integration of increasingly complex optical functions for sensing applications, are driving towards more stringent requirements in terms of top silicon layer within-wafer and wafer-to-wafer uniformity, atomic-scale surface roughness, low defect density and improved crystalline material quality. In this paper, the authors report on technological advances in the 300-mm Photonics-SOI process, while benchmarking these on a 300-mm silicon photonics multi-project wafer (MPW) process run. Notably, an extensive set of silicon photonics devices and circuits will be fabricated on a matrix of 220-nm-thick 2-μm-buried oxide Photonics-SOI substrates using different Smart-Cut process windows, with optical characterization data and device performance supporting the ultimate choice of substrate technology for silicon photonics process design kits on thin-SOI platforms.

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