This paper describes the design and performance of a new high-resolution 35 mm format CCD image sensor using an
advanced 5.5 μm interline pixel. The pixels are arranged in a 6576 (H) × 4384 (V) format to support a 3:2 aspect ratio.
This device is part of a family of devices that share a common architecture, pixel performance, and packaging
arrangement. Unique to this device in the family is the implementation of a fast line dump structure and horizontal CCD
lateral overflow drain.
A new 5.5 &mgr;m pixel interline transfer CCD technology platform has been developed that offers significant improvements in performance while retaining the dynamic range, quantum efficiency, and responsivity available from the previous generation 7.4 µm pixel. Smear has been reduced to -100 dB, and a new quad-output architecture increases the maximum frame rate up to 120 fps for a 1 MPix sensor. This technology is now being deployed across a family of image sensors that share a common package and pin-out, facilitating faster camera design and product commercialization.
This paper describes the design and performance of two new high-resolution full-frame architecture CCD imaging devices for use in professional color, digital still-imaging applications. These devices are made using 6.8 μm pixels and contain a dual-split HCCD register with two outputs to increase frame rate. The KODAK KAF-31600 Image Sensor (31 Mp) is designed with microlenses to maximize sensitivity, whereas the KODAK KAF-39000 Image Sensor (39 Mp) is designed without microlenses to maximize incident light-angle response. Of particular interest is the implementation of an under-the-field oxide (UFOX) lateral overflow drain (LOD) and thin light shield process technologies. The new UFOX LOD structure forms the LOD under the thick-field oxide that eliminates a breakdown condition, allowing much higher LOD doping levels to be used. The net result is that the LOD may be scaled to smaller dimensions, thereby enabling larger charge capacities without compromising blooming control. The thin light shield process utilizes only the TiW portion of the TiW/Al metal bilayer to form the pixel aperture. This reduces the overall stack height that helps improve angle response (for pixels using microlenses) or critical crosstalk angles (for pixels without microlenses).
In full-frame image sensors, lateral overflow drain (LOD) structures are typically formed along the vertical CCD shift registers to provide a means for preventing charge blooming in the imager pixels. In a conventional LOD structure, the n-type LOD implant is made through the thin gate dielectric stack in the device active area and adjacent to the thick field oxidation that isolates the vertical CCD columns of the imager. In this paper, a novel LOD structure is described in which the n-type LOD impurities are placed directly under the field oxidation and are, therefore, electrically isolated from the gate electrodes. By reducing the electrical fields that cause breakdown at the silicon surface, this new structure permits a larger amount of n-type impurities to be implanted for the purpose of increasing the LOD conductivity. As a consequence of the improved conductance, the LOD width can be significantly reduced, enabling the design of higher resolution imaging arrays without sacrificing charge capacity in the pixels. Numerical simulations with MEDICI of the LOD leakage current are presented that identify the breakdown mechanism, while three-dimensional solutions to Poisson's equation are used to determine the charge capacity as a function of pixel dimension.
Antonio Ciccarelli, William Davis, William Des Jardin, Hung Doan, Eric Meisenzahl, Laurel Pace, Gloria Putnam, Joseph Shepherd, Eric Stevens, Joseph Summa, Keith Wetzel
A high sensitivity front-illuminated charge-coupled device (CCD) technology has been developed by combining the transparent gate technology introduced by Kodak in 1999 with the microlens technology usually employed on interline CCDs. In this new architecture, the microlens is used to focus the incoming light onto the more transparent of the two electrodes. The new sensors offer significant increases in quantum efficiency while maintaining the performance advantages of front-illuminated full-frame CCDs including 3 pA/cm2 typical dark current at 25 degree(s)C, and 55 ke full well in a 6.8 micrometers pixel.
This paper describes the performance of an advanced high- resolution full-frame architecture CCD imaging device for use in scientific, medical and other high-performance monochromatic digital still imaging applications. Of particular interest is the replacement of the polysilicon 2nd gate electrode with that of a more spectrally transparent material thereby dramatically improving device sensitivity. This has been achieved without compromising performance in other areas such as dark current, noise, transfer efficiency and, most importantly, yield.
This paper describes the performance of an advanced high- resolution full-frame architecture CCD imaging device for use in scientific, medical, and other high performance monochromatic digital still imaging applications. Of particular interest is the replacement of the polysilicon second gate electrode with that of a more spectrally transparent material, thereby dramatically improving device sensitivity. This has been achieved without compromising performance in other areas such as dark current, noise, transfer efficiency and, most importantly, yield. Devices have also been produced with and without antiblooming protection depending on an application's primary need for sensitivity or control of over-exposure conditions.
A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.
High-resolution solid-state image sensors have become readily available due to continuing advances in VLSI technology. The authors have developed a 1.6 megapixel full-frame CCD image sensor (KAF-1600) with a 3:2 aspect ratio to meet industrial and scientific applications. The high-resolution sensor, measuring 1.55 cm X 1.0 cm, consists of 1536 X 1024 pixels. The pixel size is 9 microns X 9 microns. The sensor has a single-readout register with the capability of a 2-to-1 line charge summing. The architecture and results of the megapixel image sensor are presented.
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