Dr. David M. Owen Profile

Dr. David M. Owen

at KLA Corp

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Author

Publications (5)

Proceedings Article | 26 March 2019 Paper

Intra-field stress impact on global wafer deformation

Richard van Haren, Ronald Otten, Subodh Singh, Amandev Singh, Leon van Dijk, David Owen, Doug Anberg, Jeffrey Mileham, Yajun Gu, Jan Hermans

Proceedings Volume 10959, 109591I (2019) https://doi.org/10.1117/12.2515391

KEYWORDS: Semiconducting wafers, Distortion, Scanners, Optical alignment, Silicon, Overlay metrology, Etching, Performance modeling, Silicon films, Annealing

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One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer alignment functionality addresses the random part that is varying from wafer-to-wafer.

In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years.

In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.

Proceedings Article | 28 March 2017 Paper

Wafer-shape based in-plane distortion predictions using superfast 4G metrology

Leon van Dijk, Jeffrey Mileham, Ilja Malakhovsky, David Laidler, Harold Dekkers, Sven Van Elshocht, Doug Anberg, David Owen, Richard van Haren

Proceedings Volume 10145, 101452L (2017) https://doi.org/10.1117/12.2257475

KEYWORDS: Lithographic process control, Forward error correction, Distortion, Lithographic metrology, Semiconducting wafers, Overlay metrology, Scanners, Metrology, Thin films, Process control, Silicon films, Semiconductor manufacturing

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Proceedings Article | 24 March 2016 Paper

Study of correlation between overlay and displacement measured by Coherent Gradient Sensing (CGS) interferometry

Jeffrey Mileham, Yasushi Tanaka, Doug Anberg, David Owen, Byoung-Ho Lee, Eric Bouche

Proceedings Volume 9778, 97782W (2016) https://doi.org/10.1117/12.2220531

KEYWORDS: Overlay metrology, Lithography, Process control, Interferometry, Optical lithography, Semiconductors, Distortion, High volume manufacturing, Semiconducting wafers, Data modeling, Scanners

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Proceedings Article | 8 March 2016 Paper

Process tool monitoring and matching using interferometry technique

Doug Anberg, David Owen, Jeffrey Mileham, Byoung-Ho Lee, Eric Bouche

Proceedings Volume 9778, 977831 (2016) https://doi.org/10.1117/12.2220479

KEYWORDS: Interferometry, Semiconducting wafers, Process control, Semiconductors, Inspection, Overlay metrology, Scanners, Interferometers, Defect inspection, Manufacturing, Control systems, Image processing

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Proceedings Article | 10 April 2013 Paper

Stress inspection for overlay characterization

David Owen

Proceedings Volume 8681, 86812T (2013) https://doi.org/10.1117/12.2025310

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Inspection, Interferometers, Thin films, Phase shifting, Metrology, Data acquisition, Annealing

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