Optical refractive index (RI) sensors exploiting selective co-integration of plasmonics with silicon photonics in Lab-on-achip configurations are expected to disrupt Point-of-Care (POC) diagnostics, delivering performance and economic breakthroughs. Propagating surface-plasmon-polariton modes offer superior sensitivity due to their extreme overlap with the surrounding medium. In parallel, low-loss photonics act as the hosting platform with which the plasmonic losses can be sustained while allowing for multiplexed layouts via in-plane SPP excitation schemes. However, merging plasmonics with silicon photonics in a cost-effective manner, requires a truly CMOS-compatible manufacturing process. Herein, we demonstrate experimentally, the highest bulk-sensitivity among all the plasmo-photonic interferometric RI sensors, while taking the leap forward in the development of a CMOS-manufactured plasmo-photonic sensing platform merging Si3N4 photonics and aluminum plasmonics. The proposed structure relies on a butt-coupled interface between Si3N4 waveguides and a 70 μm long plasmonic stripe, deployed in one branch of a Mach-Zehnder Interferometer (MZI) serving as the sensing transducer that detects local changes in the refractive index. The lower MZI arm (reference arm) exploits the low-loss Si3N4 platform to deploy a MZI-based variable optical attenuator followed by a thermo-optic phase shifter to optimize the sensor performance achieving resonance extinction ratio values at the MZI output of more than 35 dB. Experimental evaluation of a gold-based sensor revealed a bulk refractive index sensitivity of 1930 nm/RIU. In addition, we experimentally demonstrate that the proposed plasmo-photonic waveguide platform can migrate from gold (Au) to Aluminum (Al), demonstrating the first step towards a fully CMOS compatible plasmo-photonic interferometric sensor.
Plasmonic sensors, leveraging the profound exposure of propagating Surface-Plasmon-Polariton (SPP) modes over metal stripes to test analytes, became so far the “gold-standard” in plasmonic biosensing resulting in commercial available devices. However, a series of challenges associated with their bulky prism-based coupling configuration as well as their high optical losses need to be overcome in order to allow for miniaturized and multiplexed sensor layouts. In this context, selective co-integration of plasmonics with low-loss silicon-nitride photonics emerges as a promising solution towards addressing these challenges yet reaping the benefits from both technologies. In this work, we present an interferometric sensor based on a Mach-Zehnder device, where a “plasmo-photonic” waveguide branch is utilized to interrogate changes in the refractive index of a test analyte exploiting the accumulated phase change of the SPP mode being exposed in an aqueous solution. More specifically, the “plasmo-photonic” Mach-Zehnder sensor incorporates a gold plasmonic stripe with a length of 70 μm and a width of 7 μm that has been interfaced with Si3N4 waveguides by means of a butt-coupled interface. By conducting numerical simulations and considering the dispersion properties of the involved materials, we optimized the structural parameters of the sensor aiming at ultra-high bulk sensitivity in the order of micrometres per Refractive Index Unit (RIU).
Publisher’s Note: This conference presentation, originally published on 14 December 2017, was withdrawn per author request
Silicon photonics meet most fabrication requirements of standard CMOS process lines encompassing the photonics-electronics consolidation vision. Despite this remarkable progress, further miniaturization of PICs for common integration with electronics and for increasing PIC functional density is bounded by the inherent diffraction limit of light imposed by optical waveguides. Instead, Surface Plasmon Polariton (SPP) waveguides can guide light at sub-wavelength scales at the metal surface providing unique light-matter interaction properties, exploiting at the same time their metallic nature to naturally integrate with electronics in high-performance ASPICs.
In this article, we demonstrate the main goals of the recently introduced H2020 project PlasmoFab towards addressing the ever increasing needs for low energy, small size and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of plasmonics with photonic and supporting electronic. We demonstrate recent advances on the hosting SiN photonic hosting platform reporting on low-loss passive SiN waveguide and Grating Coupler circuits for both the TM and TE polarization states. We also present experimental results of plasmonic gold thin-film and hybrid slot waveguide configurations that can allow for high-sensitivity sensing, providing also the ongoing activities towards replacing gold with Cu, Al or TiN metal in order to yield the same functionality over a CMOS metallic structure. Finally, the first experimental results on the co-integrated SiN+plasmonic platform are demonstrated, concluding to an initial theoretical performance analysis of the CMOS plasmo-photonic biosensor that has the potential to allow for sensitivities beyond 150000nm/RIU.
Bringing photonics and electronics into a common integration platform can unleash unprecedented performance capabilities in data communication and sensing applications. Plasmonics were proposed as the key technology that can merge ultra-fast photonics and low-dimension electronics due to their metallic nature and their unique ability to guide light at sub-wavelength scales. However, inherent high losses of plasmonics in conjunction with the use of CMOS incompatible metals like gold and silver which are broadly utilized in plasmonic applications impede their broad utilization in Photonic Integrated Circuits (PICs). To overcome those limitations and fully exploit the profound benefits of plasmonics, they have to be developed along two technology directives. 1) Selectively co-integrate nanoscale plasmonics with low-loss photonics and 2) replace noble metals with alternative CMOS-compatible counterparts accelerating volume manufacturing of plasmo-photonic ICs. In this context, a hybrid plasmo-photonic structure utilizing the CMOS-compatible metals Aluminum (Al) and Copper (Cu) is proposed to efficiently transfer light between a low-loss Si3N4 photonic waveguide and a hybrid plasmonic slot waveguide. Specifically, a Si3N4 strip waveguide (photonic part) is located below a metallic slot (plasmonic part) forming a hybrid structure. This configuration, if properly designed, can support modes that exhibit quasi even or odd symmetry allowing power exchange between the two parts. According to 3D FDTD simulations, the proposed directional coupling scheme can achieve coupling efficiencies at 1550nm up to 60% and 74% in the case of Al and Cu respectively within a coupling length of just several microns.
Plasmonic technology has attracted intense research interest enhancing the functional portfolio of photonic integrated circuits (PICs) by providing Surface-Plasmon-Polariton (SPP) modes with ultra-high confinement at sub-wavelength scale dimensions and as such increased light matter interaction. However, in most cases plasmonic waveguides rely mainly on noble metals and exhibit high optical losses, impeding their employment in CMOS processes and their practical deployment in highly useful PICs. Hence, merging CMOS compatible plasmonic waveguides with low-loss photonics by judiciously interfacing these two waveguide platforms appears as the most promising route towards the rapid and costefficient manufacturing of high-performance plasmo-photonic integrated circuits. In this work, we present butt-coupled plasmo-photonic interfaces between CMOS compatible 7μm-wide Aluminum (Al) and Copper (Cu) metal stripes and 360×800nm Si3N4 waveguides. The interfaces have been designed by means of 3D FDTD and have been optimized for aqueous environment targeting their future employment in biosensing interferometric arrangements, with the photonic waveguides being cladded with 660nm of Low Temperature Oxide (LTO) and the plasmonic stripes being recessed in a cavity formed between the photonic waveguides. The geometrical parameters of the interface will be presented based on detailed simulation results, using experimentally verified plasmonic properties for the employed CMOS metals. Numerical simulations dictated a coupling efficiency of 53% and 68% at 1.55μm wavelength for Al and Cu, respectively, with the plasmonic propagation length Lspp equaling 66μm for Al and 75μm for Cu with water considered as the top cladding. The proposed interface configuration is currently being fabricated for experimental verification.
In this paper key challenges posed on metrology by feature dimensions of 20nm and below are discussed. In detail, the need for software-based tools for SEM image acquisition and image analysis in environments where CD-SEMs are not available and/or not flexible enough to cover all inspection tasks is outlined. These environments include research at universities as well as industrial R and D environments focused on non-IC applications. The benefits of combining automated image acquisition and analysis with computational techniques to simulate image generation in a conventional analytical SEM with respect to the overall reliability, precision and speed of inspection will be demonstrated using real-life inspection tasks as demonstrators.
In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today’s low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.
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