Presentation
10 April 2024 Preliminary qualification of 3D nanoimprint process for dual damascene wiring.
Masaki Mitsuyasu, Norikazu Takeuchi, Masanori Hirose, Shunsuke Honda, Akihiko Ando, Toshiaki Komukai, Motofumi Komori, Takuya Kono
Author Affiliations +
Abstract
Nanoimprint lithography (NIL) is considered to be a sustainable technology for fabricating fine patterns and 3D structure of semiconductor devices. In this paper, we report preliminary results of device qualification for dual damascene structure fabricated by NIL. We have optimized NIL conditions to improve defectivity and overlay accuracy, and etching condition to improve fidelity and uniformity of 3D shape on the entire wafer. The 1st electrical characteristic results confirm the possibilities of one step fabrication of 3D dual damascene structure using NIL
Conference Presentation
© (2024) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Masaki Mitsuyasu, Norikazu Takeuchi, Masanori Hirose, Shunsuke Honda, Akihiko Ando, Toshiaki Komukai, Motofumi Komori, and Takuya Kono "Preliminary qualification of 3D nanoimprint process for dual damascene wiring.", Proc. SPIE PC12956, Novel Patterning Technologies 2024, PC129560G (10 April 2024); https://doi.org/10.1117/12.3010093
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KEYWORDS
Nanoimprint lithography

Etching

High volume manufacturing

Line edge roughness

Optical lithography

Overlay metrology

Semiconducting wafers

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