Dynamic power management of network-on-chip

Stefano Gigli; Luca Casagrande Montesi; Andrea Primavera; Massimo Conti

doi:10.1117/12.821665

28 May 2009 Dynamic power management of network-on-chip

Stefano Gigli, Luca Casagrande Montesi, Andrea Primavera, Massimo Conti

Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630O (2009) https://doi.org/10.1117/12.821665
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

Systems on Chip performances in terms of speed and power dissipation is becoming dominated by communication between the cores. To overcome the limitations of traditional bus architectures, nowadays Network-on-Chip architectures are adopted. The Dynamic Power Management architecture and algorithm and Network-on-Chip topology and routing algorithms should be selected considering that they both effect in a complex and complementary way the network throughput and power dissipation. This paper presents the analysis of the effect of Dynamic Power Management strategies on Network-on-Chip performances.

Citation Download Citation

Stefano Gigli, Luca Casagrande Montesi, Andrea Primavera, and Massimo Conti "Dynamic power management of network-on-chip", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630O (28 May 2009); https://doi.org/10.1117/12.821665

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