Cache-aware network-on-chip for chip multiprocessors

Konstantinos Tatas; Costas Kyriacou; George Dekoulis; Demetris Demetriou; Costas Avraam; Anastasia Christou

doi:10.1117/12.821695

28 May 2009 Cache-aware network-on-chip for chip multiprocessors

Konstantinos Tatas, Costas Kyriacou, George Dekoulis, Demetris Demetriou, Costas Avraam, Anastasia Christou

Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630N (2009) https://doi.org/10.1117/12.821695
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

Citation Download Citation

Konstantinos Tatas, Costas Kyriacou, George Dekoulis, Demetris Demetriou, Costas Avraam, and Anastasia Christou "Cache-aware network-on-chip for chip multiprocessors", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630N (28 May 2009); https://doi.org/10.1117/12.821695

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