Paper
4 December 2008 Developing loading effect on lithography I-line process
Thomas Huang, Walter Wang, Chun-Yen Huang, Nick Tseng, Ting-Jhen Guo, Chiang-Lin Shih, Wen-Bin Wu
Author Affiliations +
Proceedings Volume 7140, Lithography Asia 2008; 71403J (2008) https://doi.org/10.1117/12.804659
Event: SPIE Lithography Asia - Taiwan, 2008, Taipei, Taiwan
Abstract
With recently semiconductor manufacturers Critical Dimension shrink down to 70nm and beyond, I-line layer CD would approach to it's resolution limitation. CD uniformity controling will be strongly influenced by developing process. Regarding I-line layer developing process, CD uniformity is always varying with various developing parameters setting (as nozzle design, developing time, pulse spin, etc).
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Thomas Huang, Walter Wang, Chun-Yen Huang, Nick Tseng, Ting-Jhen Guo, Chiang-Lin Shih, and Wen-Bin Wu "Developing loading effect on lithography I-line process", Proc. SPIE 7140, Lithography Asia 2008, 71403J (4 December 2008); https://doi.org/10.1117/12.804659
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Cited by 2 scholarly publications.
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KEYWORDS
Critical dimension metrology

Semiconducting wafers

Reticles

Lithography

Photomasks

Current controlled current source

Manufacturing

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